Semiconductor device fabrication

From Wikipedia, the free encyclopedia

https://en.wikipedia.org/wiki/Semiconductor_device_fabrication 

 

Semiconductor device fabrication
MOSFET scaling (process nodes)
10 µm – 1971 6 µm – 1974 3 µm – 1977  1.5 µm – 1981 1 µm – 1984 800 nm – 1987 600 nm – 1990 350 nm – 1993 250 nm – 1996 180 nm – 1999 130 nm – 2001 90 nm – 2003 65 nm – 2005 45 nm – 2007 32 nm – 2009 22 nm – 2012 14 nm – 2014 10 nm – 2016 7 nm – 2018 5 nm – 2020
Future 3 nm ~ 2023 2 nm ~ 2024
Half-nodes Density CMOS Device (multi-gate) Moore's law Transistor count Semiconductor Industry Nanoelectronics

NASA's Glenn Research Center clean room

Semiconductor device fabrication is the process used to manufacture semiconductor devices, typically the metal–oxide–semiconductor (MOS) devices used in the integrated circuit (IC) chips such as modern computer processors, microcontrollers, and memory chips such as NAND flash and DRAM that are present in everyday electrical and electronic devices. It is a multiple-step sequence of photolithographic and chemical processing steps (such as surface passivation, thermal oxidation, planar diffusion and junction isolation) during which electronic circuits are gradually created on a wafer made of pure semiconducting material. Silicon is almost always used, but various compound semiconductors are used for specialized applications.

The entire manufacturing process takes time, from start to packaged chips ready for shipment, at least six to eight weeks (tape-out only, not including the circuit design) and is performed in highly specialized semiconductor fabrication plants, also called foundries or fabs. All fabrication takes place inside a clean room, which is the central part of a fab. In more advanced semiconductor devices, such as modern 14/10/7 nm nodes, fabrication can take up to 15 weeks, with 11–13 weeks being the industry average. Production in advanced fabrication facilities is completely automated and carried out in a hermetically sealed nitrogen environment to improve yield (the percent of microchips that function correctly in a wafer), with automated material handling systems taking care of the transport of wafers from machine to machine. Wafers are transported inside FOUPs, special sealed plastic boxes. All machinery and FOUPs contain an internal nitrogen atmosphere. The air inside the machinery and FOUPs is usually kept cleaner than the surrounding air in the cleanroom. This internal atmosphere is known as a mini-environment. Fabrication plants need large amounts of liquid nitrogen to maintain the atmosphere inside production machinery and FOUPs, which is constantly purged with nitrogen.

Size

A specific semiconductor process has specific rules on the minimum size and spacing for features on each layer of the chip. Often a newer semiconductor processes has smaller minimum sizes and tighter spacing which allow a simple die shrink to reduce costs and improve performance. partly due to an increase in transistor density (number of transistors per square millimeter). Early semiconductor processes had arbitrary names such as HMOS III, CHMOS V; later ones are referred to by size such as 90 nm process.

By industry standard, each generation of the semiconductor manufacturing process, also known as technology node or process node, is designated by the process’s minimum feature size. Technology nodes, also known as "process technologies" or simply "nodes", are typically indicated by the size in nanometers (or historically micrometers) of the process' transistor gate length. However, this has not been the case since 1994. Initially transistor gate length was smaller than that suggested by the process node name (e.g. 350 nm node); however this trend reversed in 2009. The nanometers used to name process nodes has become more of a marketing term that has no relation with actual feature sizes nor transistor density (number of transistors per square millimeter). For example, Intel's former 10 nm process actually has features (the tips of FinFET fins) with a width of 7 nm, Intel's former 10 nm process is similar in transistor density to TSMC's 7 nm processes, while GlobalFoundries' 12 and 14 nm processes have similar feature sizes.

History

See also: List of semiconductor scale examples, Moore's law, MOS integrated circuit, Semiconductor industry, and Transistor density

20th century

The first metal–oxide–silicon field-effect transistors (MOSFETs) were fabricated by Egyptian engineer Mohamed M. Atalla and Korean engineer Dawon Kahng at Bell Labs between 1959 and 1960. There were originally two types of MOSFET technology, PMOS (p-type MOS) and NMOS (n-type MOS). Both types were developed by Atalla and Kahng when they originally invented the MOSFET, fabricating both PMOS and NMOS devices at 20 µm and 10 µm scales.

An improved type of MOSFET technology, CMOS, was developed by Chih-Tang Sah and Frank Wanlass at Fairchild Semiconductor in 1963. CMOS was commercialised by RCA in the late 1960s. RCA commercially used CMOS for its 4000-series integrated circuits in 1968, starting with a 20 µm process before gradually scaling to a 10 µm process over the next several years.

Semiconductor device manufacturing has since spread from Texas and California in the 1960s to the rest of the world, including Asia, Europe, and the Middle East.

21st century

The semiconductor industry is a global business today. The leading semiconductor manufacturers typically have facilities all over the world. Samsung Electronics, the world's largest manufacturer of semiconductors, has facilities in South Korea and the US. Intel, the second-largest manufacturer, has facilities in Europe and Asia as well as the US. TSMC, the world's largest pure play foundry, has facilities in Taiwan, China, Singapore, and the US. Qualcomm and Broadcom are among the biggest fabless semiconductor companies, outsourcing their production to companies like TSMC. They also have facilities spread in different countries.

Since 2009, "node" has become a commercial name for marketing purposes that indicates new generations of process technologies, without any relation to gate length, metal pitch or gate pitch. For example, GlobalFoundries' 7 nm process is similar to Intel's 10 nm process, thus the conventional notion of a process node has become blurred. Additionally, TSMC and Samsung's 10 nm processes are only slightly denser than Intel's 14 nm in transistor density. They are actually much closer to Intel's 14 nm process than they are to Intel's 10 nm process (e.g. Samsung's 10 nm processes' fin pitch is the exact same as that of Intel's 14 nm process: 42 nm).

As of 2019, 14 nanometer and 10 nanometer chips are in mass production by Intel, UMC, TSMC, Samsung, Micron, SK Hynix, Toshiba Memory and GlobalFoundries, with 7 nanometer process chips in mass production by TSMC and Samsung, although their 7 nanometer node definition is similar to Intel's 10 nanometer process. The 5 nanometer process began being produced by Samsung in 2018. As of 2019, the node with the highest transistor density is TSMC's 5 nanometer N5 node, with a density of 171.3 million transistors per square millimeter. In 2019, Samsung and TSMC announced plans to produce 3 nanometer nodes. GlobalFoundries has decided to stop the development of new nodes beyond 12 nanometers in order to save resources, as it has determined that setting up a new fab to handle sub-12 nm orders would be beyond the company's financial abilities. As of 2019, Samsung is the industry leader in advanced semiconductor scaling, followed by TSMC and then Intel.

List of steps

This is a list of processing techniques that are employed numerous times throughout the construction of a modern electronic device; this list does not necessarily imply a specific order. Equipment for carrying out these processes is made by a handful of companies. All equipment needs to be tested before a semiconductor fabrication plant is started. These processes are done after integrated circuit design.

• Wafer processing
  • Wet cleans
    • Cleaning by solvents such as acetone, trichloroethylene and ultrapure water
    • Piranha solution
    • RCA clean
  • Surface passivation
  • Photolithography
  • Ion implantation (in which dopants are embedded in the wafer creating regions of increased or decreased conductivity)
  • Etching (microfabrication)
    • Dry etching (Plasma etching)
      • Reactive-ion etching (RIE)
        • Deep reactive-ion etching
        • Atomic layer etching (ALE)
    • Wet etching
      • Buffered oxide etch
  • Plasma ashing
  • Thermal treatments
    • Rapid thermal anneal
    • Furnace anneals
    • Thermal oxidation
  • Chemical vapor deposition (CVD)
  • Atomic layer deposition (ALD)
  • Physical vapor deposition (PVD)
  • Molecular beam epitaxy (MBE)
  • Laser lift-off (for LED production)
  • Electrochemical deposition (ECD). See Electroplating
  • Chemical-mechanical polishing (CMP)
  • Wafer testing (where the electrical performance is verified using Automatic Test Equipment, binning and/or laser trimming may also be carried out at this step)
• Die preparation
  • Through-silicon via manufacture (For three-dimensional integrated circuits)
  • Wafer mounting (wafer is mounted onto a metal frame using Dicing tape)
  • Wafer backgrinding and polishing (reduces the thickness of the wafer for thin devices like a smartcard or PCMCIA card or wafer bonding and stacking, this can also occur during wafer dicing, in a process known as Dice Before Grind or DBG)
  • Wafer bonding and stacking (For Three-dimensional integrated circuits and MEMS)
  • Redistribution layer manufacture (for WLCSP packages)
  • Wafer Bumping (For Flip chip BGA (Ball grid array), and WLCSP packages)
  • Die cutting or Wafer dicing
• IC packaging
  • Die attachment (The die is attached to a leadframe using conductive paste or die attach film)
  • IC bonding: Wire bonding, Thermosonic bonding, Flip chip or Tape Automated Bonding (TAB)
  • IC encapsulation or integrated heat spreader (IHS) installation
    • Molding (using special Molding compound that may contain glass powder as filler)
    • Baking
    • Electroplating (plates the copper leads of the lead frames with tin to make soldering easier)
    • Laser marking or silkscreen printing
    • Trim and form (separates the lead frames from each other, and bends the lead frame's pins so that they can be mounted on a Printed circuit board)
• IC testing

Additionally steps such as Wright etch may be carried out.

Progress of miniaturization, and comparison of sizes of semiconductor manufacturing process nodes with some microscopic objects and visible light wavelengths.

Prevention of contamination and defects

Main article: Cleanroom

When feature widths were far greater than about 10 micrometres, semiconductor purity was not as big of an issue as it is today in device manufacturing. As devices become more integrated, cleanrooms must become even cleaner. Today, fabrication plants are pressurized with filtered air to remove even the smallest particles, which could come to rest on the wafers and contribute to defects. The ceilings of semiconductor cleanrooms have fan filter units (FFUs) at regular intervals to constantly replace and filter the air in the cleanroom; semiconductor capital equipment may also have their own FFUs. The FFUs, combined with raised floors with grills, help ensure a laminar air flow, to ensure that particles are immediately brought down to the floor and do not stay suspended in the air due to turbulence. The workers in a semiconductor fabrication facility are required to wear cleanroom suits to protect the devices from human contamination. To prevent oxidation and to increase yield, FOUPs and semiconductor capital equipment may have a hermetically sealed pure nitrogen environment with ISO class 1 level of dust. FOUPs and SMIF pods isolate the wafers from the air in the cleanroom, increasing yield because they reduce the number of defects caused by dust particles. Also, fabs have as few people as possible in the cleanroom to make maintaining the cleanroom environment easier, since people, even when wearing cleanroom suits, shed large amounts of particles, especially when walking.

Wafers

Main articles: Wafer (electronics) and mono-crystalline silicon

A typical wafer is made out of extremely pure silicon that is grown into mono-crystalline cylindrical ingots (boules) up to 300 mm (slightly less than 12 inches) in diameter using the Czochralski process. These ingots are then sliced into wafers about 0.75 mm thick and polished to obtain a very regular and flat surface.

Processing

See also: Wafer fabrication

In semiconductor device fabrication, the various processing steps fall into four general categories: deposition, removal, patterning, and modification of electrical properties.

• Deposition is any process that grows, coats, or otherwise transfers a material onto the wafer. Available technologies include physical vapor deposition (PVD), chemical vapor deposition (CVD), electrochemical deposition (ECD), molecular beam epitaxy (MBE), and more recently, atomic layer deposition (ALD) among others. Deposition can be understood to include oxide layer formation, by thermal oxidation or, more specifically, LOCOS.
• Removal is any process that removes material from the wafer; examples include etch processes (either wet or dry) and chemical-mechanical planarization (CMP).
• Patterning is the shaping or altering of deposited materials, and is generally referred to as lithography. For example, in conventional lithography, the wafer is coated with a chemical called a photoresist; then, a machine called a stepper focuses, aligns, and moves a mask, exposing select portions of the wafer below to short-wavelength light; the exposed regions are washed away by a developer solution. After etching or other processing, the remaining photoresist is removed by "dry" plasma ashing (photoresist stripping or strip). The photoresist may also be removed using wet chemical processes that coat the wafer in a liquid to remove the photoresist.
• Modification of electrical properties has historically entailed doping transistor sources and drains (originally by diffusion furnaces and later by ion implantation). These doping processes are followed by furnace annealing or, in advanced devices, by rapid thermal annealing (RTA); annealing serves to activate the implanted dopants. Modification of electrical properties now also extends to the reduction of a material's dielectric constant in low-k insulators via exposure to ultraviolet light in UV processing (UVP). Modification is frequently achieved by oxidation, which can be carried out to create semiconductor-insulator junctions, such as in the local oxidation of silicon (LOCOS) to fabricate metal oxide field effect transistors.

Modern chips have up to eleven or more metal levels produced in over 300 or more sequenced processing steps.

Front-end-of-line (FEOL) processing

Main article: FEOL

FEOL processing refers to the formation of the transistors directly in the silicon. The raw wafer is engineered by the growth of an ultrapure, virtually defect-free silicon layer through epitaxy. In the most advanced logic devices, prior to the silicon epitaxy step, tricks are performed to improve the performance of the transistors to be built. One method involves introducing a straining step wherein a silicon variant such as silicon-germanium (SiGe) is deposited. Once the epitaxial silicon is deposited, the crystal lattice becomes stretched somewhat, resulting in improved electronic mobility. Another method, called silicon on insulator technology involves the insertion of an insulating layer between the raw silicon wafer and the thin layer of subsequent silicon epitaxy. This method results in the creation of transistors with reduced parasitic effects.

Gate oxide and implants

Main articles: self-aligned gate and doping (semiconductor)

Front-end surface engineering is followed by growth of the gate dielectric (traditionally silicon dioxide), patterning of the gate, patterning of the source and drain regions, and subsequent implantation or diffusion of dopants to obtain the desired complementary electrical properties. In dynamic random-access memory (DRAM) devices, storage capacitors are also fabricated at this time, typically stacked above the access transistor (the now defunct DRAM manufacturer Qimonda implemented these capacitors with trenches etched deep into the silicon surface).

Back-end-of-line (BEOL) processing

Main article: BEOL

Metal layers

Once the various semiconductor devices have been created, they must be interconnected to form the desired electrical circuits. This occurs in a series of wafer processing steps collectively referred to as BEOL (not to be confused with back end of chip fabrication, which refers to the packaging and testing stages). BEOL processing involves creating metal interconnecting wires that are isolated by dielectric layers. The insulating material has traditionally been a form of SiO₂ or a silicate glass, but recently new low dielectric constant materials are being used (such as silicon oxycarbide), typically providing dielectric constants around 2.7 (compared to 3.82 for SiO₂), although materials with constants as low as 2.2 are being offered to chipmakers. High-κ dielectrics may instead be used.

Interconnect

Main article: interconnect (integrated circuits)

 

Synthetic detail of a standard cell through four layers of planarized copper interconnect, down to the polysilicon (pink), wells (greyish) and substrate (green).

Historically, the metal wires have been composed of aluminum. In this approach to wiring (often called subtractive aluminum), blanket films of aluminum are deposited first, patterned, and then etched, leaving isolated wires. Dielectric material is then deposited over the exposed wires. The various metal layers are interconnected by etching holes (called "vias") in the insulating material and then depositing tungsten in them with a CVD technique using tungsten hexafluoride; this approach is still used in the fabrication of many memory chips such as dynamic random-access memory (DRAM), because the number of interconnect levels is small (currently no more than four).

More recently, as the number of interconnect levels for logic has substantially increased due to the large number of transistors that are now interconnected in a modern microprocessor, the timing delay in the wiring has become so significant as to prompt a change in wiring material (from aluminum to copper interconnect layer) and a change in dielectric material (from silicon dioxides to newer low-K insulators). This performance enhancement also comes at a reduced cost via damascene processing, which eliminates processing steps. As the number of interconnect levels increases, planarization of the previous layers is required to ensure a flat surface prior to subsequent lithography. Without it, the levels would become increasingly crooked, extending outside the depth of focus of available lithography, and thus interfering with the ability to pattern. CMP (chemical-mechanical planarization) is the primary processing method to achieve such planarization, although dry etch back is still sometimes employed when the number of interconnect levels is no more than three. Copper interconnects use an electrically conductive barrier layer to prevent the copper from diffusing into ("poisoning") its surroundings.

Wafer test

The highly serialized nature of wafer processing has increased the demand for metrology in between the various processing steps. For example, thin film metrology based on ellipsometry or reflectometry is used to tightly control the thickness of gate oxide, as well as the thickness, refractive index, and extinction coefficient of photoresist and other coatings. Wafer test metrology equipment is used to verify that the wafers haven't been damaged by previous processing steps up until testing; if too many dies on one wafer have failed, the entire wafer is scrapped to avoid the costs of further processing. Virtual metrology has been used to predict wafer properties based on statistical methods without performing the physical measurement itself.

Device test

Main article: Wafer testing

Once the front-end process has been completed, the semiconductor devices or chips are subjected to a variety of electrical tests to determine if they function properly. The percent of devices on the wafer found to perform properly is referred to as the yield. Manufacturers are typically secretive about their yields, but it can be as low as 30%, meaning that only 30% of the chips on the wafer work as intended. Process variation is one among many reasons for low yield. Testing is carried out to prevent chips from being assembled into relatively expensive packages.

The yield is often but not necessarily related to device (die or chip) size. As an example, In December 2019, TSMC announced an average yield of ~80%, with a peak yield per wafer of >90% for their 5nm test chips with a die size of 17.92 mm². The yield went down to 32.0% with an increase in die size to 100 mm².

The fab tests the chips on the wafer with an electronic tester that presses tiny probes against the chip. The machine marks each bad chip with a drop of dye. Currently, electronic dye marking is possible if wafer test data (results) are logged into a central computer database and chips are "binned" (i.e. sorted into virtual bins) according to predetermined test limits such as maximum operating frequencies/clocks, number of working (fully functional) cores per chip, etc. The resulting binning data can be graphed, or logged, on a wafer map to trace manufacturing defects and mark bad chips. This map can also be used during wafer assembly and packaging. Binning allows chips that would otherwise be rejected to be reused in lower-tier products, as is the case with GPUs and CPUs, increasing device yield, especially since very few chips are fully functional (have all cores functioning correctly, for example). eFUSEs may be used to disconnect parts of chips such as cores, either because they didn't work as intended during binning, or as part of market segmentation (using the same chip for low, mid and high-end tiers). Chips may have spare parts to allow the chip to fully pass testing even if it has several non-working parts.

Chips are also tested again after packaging, as the bond wires may be missing, or analog performance may be altered by the package. This is referred to as the "final test". Chips may also be imaged using x-rays.

Usually, the fab charges for testing time, with prices in the order of cents per second. Testing times vary from a few milliseconds to a couple of seconds, and the test software is optimized for reduced testing time. Multiple chip (multi-site) testing is also possible because many testers have the resources to perform most or all of the tests in parallel and on several chips at once.

Chips are often designed with "testability features" such as scan chains or a "built-in self-test" to speed testing and reduce testing costs. In certain designs that use specialized analog fab processes, wafers are also laser-trimmed during testing, in order to achieve tightly distributed resistance values as specified by the design.

Good designs try to test and statistically manage corners (extremes of silicon behavior caused by a high operating temperature combined with the extremes of fab processing steps). Most designs cope with at least 64 corners.

Device yield

Device yield or die yield is the number of working chips or dies on a wafer, given in percentage since the number of chips on a wafer (Die per wafer, DPW) can vary depending on the chips' size and the wafer's diameter. Yield degradation is a reduction in yield, which historically was mainly caused by dust particles, however since the 1990s, yield degradation is mainly caused by process variation, the process itself and by the tools used in chip manufacturing, although dust still remains a problem in many older fabs. Dust particles have an increasing effect on yield as feature sizes are shrunk with newer processes. Automation and the use of mini environments inside of production equipment, FOUPs and SMIFs have enabled a reduction in defects caused by dust particles. Device yield must be kept high to reduce the selling price of the working chips since working chips have to pay for those chips that failed, and to reduce the cost of wafer processing. Yield can also be affected by the design and operation of the fab.

Tight control over contaminants and the production process are necessary to increase yield. Contaminants may be chemical contaminants or be dust particles. "Killer defects" are those caused by dust particles that cause complete failure of the device (such as a transistor). There are also harmless defects. A particle needs to be 1/5 the size of a feature to cause a killer defect. So if a feature is 100 nm across, a particle only needs to be 20 nm across to cause a killer defect. Electrostatic electricity can also affect yield adversely. Chemical contaminants or impurities include heavy metals such as iron, copper, nickel, zinc, chromium, gold, mercury and silver, alkali metals such as sodium, potassium and lithium, and elements such as aluminum, magnesium, calcium, chlorine, sulfur, carbon, and fluorine. It is important for these elements to not remain in contact with the silicon, as they could reduce yield. Chemical mixtures may be used to remove these elements from the silicon; different mixtures are effective against different elements.

Several models are used to estimate yield. They are Murphy's model, Poisson's model, the binomial model, Moore's model and Seeds' model. There is no universal model; a model has to be chosen based on actual yield distribution (the location of defective chips) For example, Murphy's model assumes that yield loss occurs more at the edges of the wafer (non-working chips are concentrated on the edges of the wafer), Poisson's model assumes that defective dies are spread relatively evenly across the wafer, and Seeds's model assumes that defective dies are clustered together.

Smaller dies cost less to produce (since more fit on a wafer, and wafers are processed and priced as a whole), and can help achieve higher yields since smaller dies have a lower chance of having a defect, due to their lower surface area on the wafer. However, smaller dies require smaller features to achieve the same functions of larger dies or surpass them, and smaller features require reduced process variation and increased purity (reduced contamination) to maintain high yields. Metrology tools are used to inspect the wafers during the production process and predict yield, so wafers predicted to have too many defects may be scrapped to save on processing costs.

Die preparation

Main articles: Wafer backgrinding and Die preparation

Once tested, a wafer is typically reduced in thickness in a process also known as "backlap", "backfinish" or "wafer thinning" before the wafer is scored and then broken into individual dies, a process known as wafer dicing. Only the good, unmarked chips are packaged.

Packaging

Main article: Integrated circuit packaging

Plastic or ceramic packaging involves mounting the die, connecting the die pads to the pins on the package, and sealing the die. Tiny bondwires are used to connect the pads to the pins. In the 'old days' (1970s), wires were attached by hand, but now specialized machines perform the task. Traditionally, these wires have been composed of gold, leading to a lead frame (pronounced "leed frame") of solder-plated copper; lead is poisonous, so lead-free "lead frames" are now mandated by RoHS.

Chip scale package (CSP) is another packaging technology. A plastic dual in-line package, like most packages, is many times larger than the actual die hidden inside, whereas CSP chips are nearly the size of the die; a CSP can be constructed for each die before the wafer is diced.

The packaged chips are retested to ensure that they were not damaged during packaging and that the die-to-pin interconnect operation was performed correctly. A laser then etches the chip's name and numbers on the package.

Hazardous materials

See also: Health hazards in semiconductor manufacturing occupations

Many toxic materials are used in the fabrication process. These include:

• poisonous elemental dopants, such as arsenic, antimony, and phosphorus.
• poisonous compounds, such as arsine, phosphine, tungsten hexafluoride and silane.
• highly reactive liquids, such as hydrogen peroxide, fuming nitric acid, sulfuric acid, and hydrofluoric acid.

It is vital that workers should not be directly exposed to these dangerous substances. The high degree of automation common in the IC fabrication industry helps to reduce the risks of exposure. Most fabrication facilities employ exhaust management systems, such as wet scrubbers, combustors, heated absorber cartridges, etc., to control the risk to workers and to the environment.

Glycated hemoglobin

From Wikipedia, the free encyclopedia

https://en.wikipedia.org/wiki/Glycated_hemoglobin 

 

Glycated hemoglobin
MedlinePlus	003640
eMedicine	2049478
LOINC	41995-2

Glycated hemoglobin (glycohemoglobin, hemoglobin A1c, HbA1c, less commonly HbA_1c, HgbA1c, Hb1c, etc., also A1C informally with patients) is a form of hemoglobin (Hb) that is chemically linked to a sugar. Most monosaccharides, including glucose, galactose and fructose, spontaneously (i.e. non-enzymatically) bond with hemoglobin, when present in the bloodstream of humans. However, glucose is less likely to do so than galactose and fructose (13% that of fructose and 21% that of galactose), which may explain why glucose is used as the primary metabolic fuel in humans.

The formation of the sugar-hemoglobin linkage indicates the presence of excessive sugar in the bloodstream, often indicative of diabetes. A1C is of particular interest because it is easy to detect. The process by which sugars attach to hemoglobin is called glycation. HbA_1c is a measure of the beta-N-1-deoxy fructosyl component of hemoglobin.

A1c is measured primarily to determine the three-month average blood sugar level and can be used as a diagnostic test for diabetes mellitus and as an assessment test for glycemic control in people with diabetes. The test is limited to a three-month average because the average lifespan of a red blood cell is four months. Since individual red blood cells have varying lifespans, the test is used as a limited measure of three months. Normal levels of glucose produce a normal amount of glycated hemoglobin. As the average amount of plasma glucose increases, the fraction of glycated hemoglobin increases in a predictable way. In diabetes, higher amounts of glycated hemoglobin, indicating poorer control of blood glucose levels, have been associated with cardiovascular disease, nephropathy, neuropathy, and retinopathy.

Terminology

Glycated hemoglobin is preferred over glycosylated hemoglobin to reflect the correct (non-enzymatic) process. Early literature often used glycosylated as it was unclear which process was involved until further research was performed. The terms are still sometimes used interchangeably in English-language literature.

The naming of HbA_1c derives from Hemoglobin type A being separated on cation exchange chromatography. The first fraction to separate, probably considered to be pure Hemoglobin A, was designated HbA₀, and the following fractions were designated HbA_1a, HbA_1b, and HbA_1c, in their order of elution. Improved separation techniques have subsequently led to the isolation of more subfractions.

History

Hemoglobin A1c was first separated from other forms of hemoglobin by Huisman and Meyering in 1958 using a chromatographic column. It was first characterized as a glycoprotein by Bookchin and Gallop in 1968. Its increase in diabetes was first described in 1969 by Samuel Rahbar et al. The reactions leading to its formation were characterized by Bunn and his coworkers in 1975.

The use of hemoglobin A1c for monitoring the degree of control of glucose metabolism in diabetic patients was proposed in 1976 by Anthony Cerami, Ronald Koenig and coworkers.

Damage mechanisms

Glycated hemoglobin causes an increase of highly reactive free radicals inside blood cells, altering the properties of their cell membranes. This leads to blood cell aggregation and increased blood viscosity, which results in impaired blood flow.

Another way glycated hemoglobin causes damage is via inflammation, which results in atherosclerotic plaque (atheroma) formation. Free-radical build-up promotes the excitation of Fe²⁺-hemoglobin through Fe³⁺-Hb into abnormal ferryl hemoglobin (Fe⁴⁺-Hb). Fe⁴⁺ is unstable and reacts with specific amino acids in hemoglobin to regain its Fe³⁺ oxidation state. Hemoglobin molecules clump together via cross-linking reactions, and these hemoglobin clumps (multimers) promote cell damage and the release of Fe⁴⁺-hemoglobin into the matrix of innermost layers (subendothelium) of arteries and veins. This results in increased permeability of interior surface (endothelium) of blood vessels and production of pro-inflammatory monocyte adhesion proteins, which promote macrophage accumulation in blood vessel surfaces, ultimately leading to harmful plaques in these vessels.

Highly glycated Hb-AGEs go through vascular smooth muscle layer and inactivate acetylcholine-induced endothelium-dependent relaxation, possibly through binding to nitric oxide (NO), preventing its normal function. NO is a potent vasodilator and also inhibits formation of plaque-promoting LDLs (i.e. “bad cholesterol”) oxidized form.

This overall degradation of blood cells also releases heme from them. Loose heme can cause oxidation of endothelial and LDL proteins, which results in plaques.

Glycation pathway via Amadori Rearrangement (in HbA1c, R is typically N-terminal valine).

Principle in medical diagnostics

Glycation of proteins is a frequent occurrence, but in the case of hemoglobin, a nonenzymatic condensation reaction occurs between glucose and the N-end of the beta chain. This reaction produces a Schiff base (R-N=CHR', R = beta chain, CHR'= glucose-derived), which is itself converted to 1-deoxyfructose. This second conversion is an example of an Amadori rearrangement. When blood glucose levels are high, glucose molecules attach to the hemoglobin in red blood cells. The longer hyperglycemia occurs in blood, the more glucose binds to hemoglobin in the red blood cells and the higher the glycated hemoglobin.

Once a hemoglobin molecule is glycated, it remains that way. A buildup of glycated hemoglobin within the red cell, therefore, reflects the average level of glucose to which the cell has been exposed during its life-cycle. Measuring glycated hemoglobin assesses the effectiveness of therapy by monitoring long-term serum glucose regulation.

A1c is a weighted average of blood glucose levels during the life of the red blood cells (117 days for men and 106 days in women). Therefore, glucose levels on days nearer to the test contribute substantially more to the level of A1c than the levels in days further from the test.

This is also supported by data from clinical practice showing that HbA1c levels improved significantly after 20 days from start or intensification of glucose-lowering treatment.

Measurement

Several techniques are used to measure hemoglobin A1c. Laboratories may use high-performance liquid chromatography, immunoassay, enzymatic assay, capillary electrophoresis, or boronate affinity chromatography. Point of care (e.g., doctor's office) devices use immunoassay boronate affinity chromatography.

In the United States, HbA_1c testing laboratories are certified by the National Glycohemoglobin Standardization Program to standardize them against the results of the 1993 Diabetes Control and Complications Trial (DCCT). An additional percentage scale, Mono S has previously been in use by Sweden and KO500 is in use in Japan.

Switch to IFCC units

The American Diabetes Association, European Association for the Study of Diabetes, and International Diabetes Federation have agreed that, in the future, HbA_1c is to be reported in the International Federation of Clinical Chemistry and Laboratory Medicine (IFCC) units. IFCC reporting was introduced in Europe except for the UK in 2003; the UK carried out dual reporting from 1 June 2009  until 1 October 2011.

Conversion between DCCT and IFCC is by the following equation:

${\displaystyle \mathrm {IFCC} \,\mathrm {HBA1c} \,{\frac {\text{mmol}}{\text{mol}}}=[\mathrm {DCCT} \,\mathrm {HBA1c} \,(\%)-2.14]\times 10.929}$

IFCC-HbA1c	DCCT-HbA1c	Mono S- HbA1c

Interpretation of results

Laboratory results may differ depending on the analytical technique, the age of the subject, and biological variation among individuals. Higher levels of HbA_1c are found in people with persistently elevated blood sugar, as in diabetes mellitus. While diabetic patient treatment goals vary, many include a target range of HbA_1c values. A diabetic person with good glucose control has an HbA_1c level that is close to or within the reference range.

The International Diabetes Federation and the American College of Endocrinology recommend HbA_1c values below 48 mmol/mol (6.5 DCCT %), while the American Diabetes Association recommends HbA_1c be below 53 mmol/mol (7.0 DCCT %) for most patients. Results from large trials in 2008-9 suggested that a target below 53 mmol/mol (7 DCCT %) for older adults with type 2 diabetes may be excessive: Below 53 mmol/mol, the health benefits of reduced A1c become smaller, and the intensive glycemic control required to reach this level leads to an increased rate of dangerous hypoglycemic episodes.

A retrospective study of 47,970 type 2 diabetes patients, aged 50 years and older, found that patients with an HbA_1c more than 48 mmol/mol (6.5 DCCT %) had an increased mortality rate, but a later international study contradicted these findings.

A review of the UKPDS, Action to Control Cardiovascular Risk in Diabetes (ACCORD), ADVANCE and Veterans Affairs Diabetes Trials (VADT) estimated that the risks of the main complications of diabetes (diabetic retinopathy, diabetic nephropathy, diabetic neuropathy, and macrovascular disease) decreased by about 3% for every 1 mmol/mol decrease in HbA_1c.

However, a trial by ACCORD designed specifically to determine whether reducing HbA_1c below 6.0% using increased amounts of medication would reduce the rate of cardiovascular events found higher mortality with this intensive therapy, so much so that the trial was terminated 17 months early.

Practitioners must consider patients' health, their risk of hypoglycemia, and their specific health risks when setting a target HbA_1c level. Because patients are responsible for averting or responding to their own hypoglycemic episodes, their input and the doctors' assessments of the patients' self-care skills are also important.

Persistent elevations in blood sugar (and, therefore, HbA_1c) increase the risk of long-term vascular complications of diabetes, such as coronary disease, heart attack, stroke, heart failure, kidney failure, blindness, erectile dysfunction, neuropathy (loss of sensation, especially in the feet), gangrene, and gastroparesis (slowed emptying of the stomach). Poor blood glucose control also increases the risk of short-term complications of surgery such as poor wound healing.

Lower-than-expected levels of HbA_1c can be seen in people with shortened red blood cell lifespans, such as with glucose-6-phosphate dehydrogenase deficiency, sickle-cell disease, or any other condition causing premature red blood cell death. Blood donation will result in rapid replacement of lost RBCs with newly formed red blood cells. Since these new RBCs will have only existed for a short period of time, their presence will lead HbA_1c to underestimate the actual average levels. There may also be distortions resulting from blood donation during the preceding two months, due to an abnormal synchronization of the age of the RBCs, resulting in an older than normal average blood cell life (resulting in an overestimate of actual average blood glucose levels). Conversely, higher-than-expected levels can be seen in people with a longer red blood cell lifespan, such as with iron deficiency.

Results can be unreliable in many circumstances, for example after blood loss, after surgery, blood transfusions, anemia, or high erythrocyte turnover; in the presence of chronic renal or liver disease; after administration of high-dose vitamin C; or erythropoetin treatment. In general, the reference range (that found in healthy young persons), is about 30–33 mmol/mol (4.9–5.2 DCCT %). The mean HbA_1c for diabetics type 1 in Sweden in 2014 was 63 mmol/mol (7.9 DCCT%) and for type 2, 61 mmol/mol (7.7 DCCT%).

The approximate mapping between HbA_1c values given in DCCT percentage (%) and eAG (estimated average glucose) measurements is given by the following equation:

eAG(mg/dl) = 28.7 × A1C − 46.7
eAG(mmol/l) = 1.59 × A1C − 2.59
Data in parentheses are 95% confidence intervals

HbA1c		eAG
%	mmol/mol	mmol/L	mg/dL
5	31	5.4 (4.2–6.7)	97 (76–120)
6	42	7.0 (5.5–8.5)	126 (100–152)
7	53	8.6 (6.8–10.3)	154 (123–185)
8	64	10.2 (8.1–12.1)	183 (147–217)
9	75	11.8 (9.4–13.9)	212 (170–249)
10	86	13.4 (10.7–15.7)	240 (193–282)
11	97	14.9 (12.0–17.5)	269 (217–314)
12	108	16.5 (13.3–19.3)	298 (240–347)
13	119	18.1 (15–21)	326 (260–380)
14	130	19.7 (16–23)	355 (290–410)
15	140	21.3 (17–25)	384 (310–440)
16	151	22.9 (19–26)	413 (330–480)
17	162	24.5 (20–28)	441 (460–510)
18	173	26.1 (21–30)	470 (380–540)
19	184	27.7 (23–32)	499 (410–570)

Normal, prediabetic, and diabetic range

The 2010 American Diabetes Association Standards of Medical Care in Diabetes added the =HbA_1c ≥ 48 mmol/mol (≥6.5 DCCT %) as another criterion for the diagnosis of diabetes.

Diagnostic Standard for HbA1C in Diabetes

HbA1C	Diagnosis
<5.7%	Normal
5.7-6.4%	Prediabetes
>6.4%	Diabetes

Indications and uses

Glycated hemoglobin testing is recommended for both checking the blood sugar control in people who might be prediabetic and monitoring blood sugar control in patients with more elevated levels, termed diabetes mellitus. For a single blood sample, it provides far more revealing information on glycemic behavior than a fasting blood sugar value. However, fasting blood sugar tests are crucial in making treatment decisions. The American Diabetes Association guidelines are similar to others in advising that the glycated hemoglobin test be performed at least twice a year in patients with diabetes who are meeting treatment goals (and who have stable glycemic control) and quarterly in patients with diabetes whose therapy has changed or who are not meeting glycemic goals.

Glycated hemoglobin measurement is not appropriate where a change in diet or treatment has been made within 6 weeks. Likewise, the test assumes a normal red blood cell aging process and mix of hemoglobin subtypes (predominantly HbA in normal adults). Hence, people with recent blood loss, hemolytic anemia, or genetic differences in the hemoglobin molecule (hemoglobinopathy) such as sickle-cell disease and other conditions, as well as those who have donated blood recently, are not suitable for this test.

Due to glycated hemoglobin's variability (as shown in the table above), additional measures should be checked in patients at or near recommended goals. People with HbA_1c values at 64 mmol/mol or less should be provided additional testing to determine whether the HbA_1c values are due to averaging out high blood glucose (hyperglycemia) with low blood glucose (hypoglycemia) or the HbA_1c is more reflective of an elevated blood glucose that does not vary much throughout the day. Devices such as continuous blood glucose monitoring allow people with diabetes to determine their blood glucose levels on a continuous basis, testing every few minutes. Continuous use of blood glucose monitors is becoming more common, and the devices are covered by many health insurance plans, but not by Medicare in the United States. The supplies tend to be expensive, since the sensors must be changed at least every 2 weeks. Another useful test in determining if HbA_1c values are due to wide variations of blood glucose throughout the day is 1,5-anhydroglucitol, also known as GlycoMark. GlycoMark reflects only the times that the person experiences hyperglycemia above 180 mg/dl over a two-week period.

Concentrations of hemoglobin A1 (HbA1) are increased, both in diabetic patients and in patients with kidney failure, when measured by ion-exchange chromatography. The thiobarbituric acid method (a chemical method specific for the detection of glycation) shows that patients with kidney failure have values for glycated hemoglobin similar to those observed in normal subjects, suggesting that the high values in these patients are a result of binding of something other than glucose to hemoglobin.

In autoimmune hemolytic anemia, concentrations of HbA1 is undetectable. Administration of prednisolone will allow the HbA1 to be detected. The alternative fructosamine test may be used in these circumstances and it also reflects an average of blood glucose levels over the preceding 2 to 3 weeks.

All the major institutions such as the International Expert Committee Report, drawn from the International Diabetes Federation, the European Association for the Study of Diabetes, and the American Diabetes Association, suggest the HbA_1c level of 48 mmol/mol (6.5 DCCT %) as a diagnostic level. The Committee Report further states that, when HbA_1c testing cannot be done, the fasting and glucose-tolerance tests be done. Diagnosis of diabetes during pregnancy continues to require fasting and glucose-tolerance measurements for gestational diabetes, and not the glycated hemoglobin.

Modification by diet

Meta-analysis has shown probiotics to cause a statistically significant reduction in glycated hemoglobin in type 2 diabetics. Trials with multiple strains of probiotics had statistically significant reductions in glycated hemoglobin, whereas trials with single strains did not.

Standardization and traceability

Hemoglobin A1c is now standardized and traceable to IFCC methods HPLC-CE and HPLC-MS. The change to the newer unit of mmol/mol is part of this standardization. The standardized test does not test for iodine levels in the blood; hypothyroidism or iodine supplementation are known to artificially raise the A1c.

Veterinary medicine

HbA1c testing has not been found useful in the treatment of cats and dogs with diabetes, and is not generally used; fructosamine is favoured instead.