Semiconductor device fabrication

From Wikipedia, the free encyclopedia

 

 

Semiconductor device fabrication
MOSFET scaling (process nodes)
10 µm – 1971 6 µm – 1974 3 µm – 1977  1.5 µm – 1981 1 µm – 1984 800 nm – 1987 600 nm – 1990 350 nm – 1993 250 nm – 1996 180 nm – 1999 130 nm – 2001 90 nm – 2003 65 nm – 2005 45 nm – 2007 32 nm – 2009 22 nm – 2012 14 nm – 2014 10 nm – 2016 7 nm – 2018 5 nm – 2020
Future 3 nm – ~2022 2 nm – ~2023
Half-nodes Density CMOS Device (multi-gate) Moore's law Semiconductor Industry Nanoelectronics

NASA's Glenn Research Center clean room

External image Photo of the interior of a clean room of a 300mm fab run by TSMC

Semiconductor device fabrication is the process used to manufacture semiconductor devices, typically the metal–oxide–semiconductor (MOS) devices used in the integrated circuit (IC) chips that are present in everyday electrical and electronic devices. It is a multiple-step sequence of photolithographic and chemical processing steps (such as surface passivation, thermal oxidation, planar diffusion and junction isolation) during which electronic circuits are gradually created on a wafer made of pure semiconducting material. Silicon is almost always used, but various compound semiconductors are used for specialized applications.

The entire manufacturing process, from start to packaged chips ready for shipment, takes six to eight weeks and is performed in highly specialized semiconductor fabrication plants, also called foundries or fabs. All fabrication takes place inside the clean rooms of these fabs. In more advanced semiconductor devices, such as modern 14/10/7 nm nodes, fabrication can take up to 15 weeks, with 11–13 weeks being the industry average. Production in advanced fabrication facilities is completely automated and carried out in a hermetically sealed nitrogen environment to improve yield (the percent of microchips that function correctly in a wafer), with automated material handling systems taking care of the transport of wafers from machine to machine. Wafers are transported inside FOUPs, special sealed plastic boxes. All machinery and FOUPs contains an internal nitrogen atmosphere. The air inside the machinery and FOUPs is usually kept cleaner than the surrounding air in the cleanroom. This internal atmosphere is known as a mini-environment. Fabrication plants need large amounts of liquid nitrogen to maintain the atmosphere inside production machinery and FOUPs, which is constantly purged with nitrogen.

Size

A specific semiconductor process has specific rules on the minimum size and spacing for features on each layer of the chip. Often a newer semiconductor processes allows a simple die shrink to reduce costs and improve performance. Early semiconductor processes had arbitrary names such as HMOS III, CHMOS V; later ones are referred to by size such as 90 nm process.

By industry standard, each generation of the semiconductor manufacturing process, also known as technology node, is designated by the process’ minimum feature size. Technology nodes, also known as "process technologies" or simply "nodes", are typically indicated by the size in nanometers (or historically micrometers) of the process' transistor gate length.

History

20th century

The first metal–oxide–silicon field-effect transistors (MOSFETs) were fabricated by Egyptian engineer Mohamed M. Atalla and Korean engineer Dawon Kahng at Bell Labs between 1959 and 1960. There were originally two types of MOSFET technology, PMOS (p-type MOS) and NMOS (n-type MOS). Both types were developed by Atalla and Kahng when they originally invented the MOSFET, fabricating both PMOS and NMOS devices at 20 µm and 10 µm scales.

An improved type of MOSFET technology, CMOS, was developed by Chih-Tang Sah and Frank Wanlass at Fairchild Semiconductor in 1963. CMOS was commercialised by RCA in the late 1960s. RCA commercially used CMOS for its 4000-series integrated circuits in 1968, starting with a 20 µm process before gradually scaling to a 10 µm process over the next several years.

Semiconductor device manufacturing has since spread from Texas and California in the 1960s to the rest of the world, including Asia, Europe, and the Middle East.

21st century

The semiconductor industry is a global business today. The leading semiconductor manufacturers typically have facilities all over the world. Samsung Electronics, the world's largest manufacturer of semiconductors, has facilities in South Korea and the US. Intel, the second-largest manufacturer, has facilities in Europe and Asia as well as the US. TSMC, the world's largest pure play foundry, has facilities in Taiwan, China, Singapore, and the US. Qualcomm and Broadcom are among the biggest fabless semiconductor companies, outsourcing their production to companies like TSMC. They also have facilities spread in different countries.

Since 2009, "node" has become a commercial name for marketing purposes that indicates new generations of process technologies, without any relation to gate length, metal pitch or gate pitch. For example, GlobalFoundries' 7 nm process is similar to Intel's 10 nm process, thus the conventional notion of a process node has become blurred. Additionally, TSMC and Samsung's 10 nm processes are only slightly denser than Intel's 14 nm in transistor density. They are actually much closer to Intel's 14 nm process than they are to Intel's 10 nm process (e.g. Samsung's 10 nm processes' fin pitch is the exact same as that of Intel's 14 nm process: 42 nm).

As of 2019, 14 nanometer and 10 nanometer chips are in mass production by Intel, UMC, TSMC, Samsung, Micron, SK Hynix, Toshiba Memory and GlobalFoundries, with 7 nanometer process chips in mass production by TSMC and Samsung, although their 7 nanometer node definition is similar to Intel's 10 nanometer process. The 5 nanometer process began being produced by Samsung in 2018. As of 2019, the node with the highest transistor density is TSMC's 5 nanometer N5 node, with a density of 171.3 million transistors per square millimeter. In 2019, Samsung and TSMC announced plans to produce 3 nanometer nodes. GlobalFoundries has decided to stop the development of new nodes beyond 12 nanometers in order to save resources, as it has determined that setting up a new fab to handle sub-12nm orders would be beyond the company's financial abilities. As of 2019, Samsung is the industry leader in advanced semiconductor scaling, followed by TSMC and then Intel.

List of steps

This is a list of processing techniques that are employed numerous times throughout the construction of a modern electronic device; this list does not necessarily imply a specific order. Equipment for carrying out these processes is made by a handful of companies. All equipment needs to be tested before a semiconductor fabrication plant is started. 

• Wafer processing
  • Wet cleans
    • Cleaning by solvents such as acetone, trichloroethylene and ultrapure water
    • Piranha solution
    • RCA clean
  • Surface passivation
  • Photolithography
  • Ion implantation (in which dopants are embedded in the wafer creating regions of increased or decreased conductivity)
  • Dry etching
    • Reactive-ion etching
  • Atomic layer etching (ALE)
  • Wet etching
  • Plasma ashing
  • Thermal treatments
    • Rapid thermal anneal
    • Furnace anneals
    • Thermal oxidation
  • Chemical vapor deposition (CVD)
  • Atomic layer deposition (ALD)
  • Physical vapor deposition (PVD)
  • Molecular beam epitaxy (MBE)
  • Laser lift-off (for LED production)
  • Electrochemical deposition (ECD). See Electroplating
  • Chemical-mechanical polishing (CMP)
  • Wafer testing (where the electrical performance is verified using Automatic Test Equipment, laser trimming may also be carried out at this step)
• Die preparation
  • Through-silicon via manufacture (For three-dimensional integrated circuits)
  • Wafer mounting (wafer is mounted onto a metal frame using Dicing tape)
  • Wafer backgrinding and polishing (reduces the thickness of the wafer for thin devices like a smartcard or PCMCIA card or wafer bonding and stacking, this can also occur during wafer dicing, in a process known as Dice Before Grind or DBG)
  • Wafer bonding and stacking (For Three-dimensional integrated circuits and MEMS)
  • Redistribution layer manufacture (for WLCSP packages)
  • Wafer Bumping (For Flip Chip BGA, and WLCSP packages)
  • Die cutting or Wafer dicing
• IC packaging
  • Die attachment (The die is attached to the leadframe using conductive paste or die attach film)
  • IC bonding: Wire bonding, Thermosonic bonding, Flip chip or Tape Automated Bonding (TAB)
  • IC encapsulation
    • Molding (using special Molding compound)
    • Baking
    • Electroplating (plates the copper leads of the lead frames with tin to make soldering easier)
    • Laser marking or silkscreen printing
    • Trim and form (separates the lead frames from each other, and bends the lead frame's pins so that they can be mounted on a Printed circuit board)
• IC testing

Progress of miniaturization, and comparison of sizes of semiconductor manufacturing process nodes with some microscopic objects and visible light wavelengths.

Prevention of contamination and defects

When feature widths were far greater than about 10 micrometres, semiconductor purity was not as big of an issue as it is today in device manufacturing. As devices become more integrated, cleanrooms must become even cleaner. Today, fabrication plants are pressurized with filtered air to remove even the smallest particles, which could come to rest on the wafers and contribute to defects. The workers in a semiconductor fabrication facility are required to wear cleanroom suits to protect the devices from human contamination. To prevent oxidation and to increase yield, FOUPs and semiconductor capital equipment may have a hermetically sealed pure nitrogen environment with ISO class 1 level of dust.

Wafers

A typical wafer is made out of extremely pure silicon that is grown into mono-crystalline cylindrical ingots (boules) up to 300 mm (slightly less than 12 inches) in diameter using the Czochralski process. These ingots are then sliced into wafers about 0.75 mm thick and polished to obtain a very regular and flat surface.

Processing

In semiconductor device fabrication, the various processing steps fall into four general categories: deposition, removal, patterning, and modification of electrical properties.

• Deposition is any process that grows, coats, or otherwise transfers a material onto the wafer. Available technologies include physical vapor deposition (PVD), chemical vapor deposition (CVD), electrochemical deposition (ECD), molecular beam epitaxy (MBE) and more recently, atomic layer deposition (ALD) among others. Deposition can be understood to include oxide layer formation, by thermal oxidation or, more specifically, LOCOS.
• Removal is any process that removes material from the wafer; examples include etch processes (either wet or dry) and chemical-mechanical planarization (CMP).
• Patterning is the shaping or altering of deposited materials, and is generally referred to as lithography. For example, in conventional lithography, the wafer is coated with a chemical called a photoresist; then, a machine called a stepper focuses, aligns, and moves a mask, exposing select portions of the wafer below to short-wavelength light; the exposed regions are washed away by a developer solution. After etching or other processing, the remaining photoresist is removed by plasma ashing.
• Modification of electrical properties has historically entailed doping transistor sources and drains (originally by diffusion furnaces and later by ion implantation). These doping processes are followed by furnace annealing or, in advanced devices, by rapid thermal annealing (RTA); annealing serves to activate the implanted dopants. Modification of electrical properties now also extends to the reduction of a material's dielectric constant in low-k insulators via exposure to ultraviolet light in UV processing (UVP). Modification is frequently achieved by oxidation, which can be carried out to create semiconductor-insulator junctions, such as in the local oxidation of silicon (LOCOS) to fabricate metal oxide field effect transistors.

Modern chips have up to eleven metal levels produced in over 300 sequenced processing steps.

Front-end-of-line (FEOL) processing

FEOL processing refers to the formation of the transistors directly in the silicon. The raw wafer is engineered by the growth of an ultrapure, virtually defect-free silicon layer through epitaxy. In the most advanced logic devices, prior to the silicon epitaxy step, tricks are performed to improve the performance of the transistors to be built. One method involves introducing a straining step wherein a silicon variant such as silicon-germanium (SiGe) is deposited. Once the epitaxial silicon is deposited, the crystal lattice becomes stretched somewhat, resulting in improved electronic mobility. Another method, called silicon on insulator technology involves the insertion of an insulating layer between the raw silicon wafer and the thin layer of subsequent silicon epitaxy. This method results in the creation of transistors with reduced parasitic effects.

Gate oxide and implants

Front-end surface engineering is followed by growth of the gate dielectric (traditionally silicon dioxide), patterning of the gate, patterning of the source and drain regions, and subsequent implantation or diffusion of dopants to obtain the desired complementary electrical properties. In dynamic random-access memory (DRAM) devices, storage capacitors are also fabricated at this time, typically stacked above the access transistor (the now defunct DRAM manufacturer Qimonda implemented these capacitors with trenches etched deep into the silicon surface).

Back-end-of-line (BEOL) processing

Metal layers

Once the various semiconductor devices have been created, they must be interconnected to form the desired electrical circuits. This occurs in a series of wafer processing steps collectively referred to as BEOL (not to be confused with back end of chip fabrication, which refers to the packaging and testing stages). BEOL processing involves creating metal interconnecting wires that are isolated by dielectric layers. The insulating material has traditionally been a form of SiO₂ or a silicate glass, but recently new low dielectric constant materials are being used (such as silicon oxycarbide), typically providing dielectric constants around 2.7 (compared to 3.82 for SiO₂), although materials with constants as low as 2.2 are being offered to chipmakers.

Interconnect

Synthetic detail of a standard cell through four layers of planarized copper interconnect, down to the polysilicon (pink), wells (greyish) and substrate (green).

Historically, the metal wires have been composed of aluminum. In this approach to wiring (often called subtractive aluminum), blanket films of aluminum are deposited first, patterned, and then etched, leaving isolated wires. Dielectric material is then deposited over the exposed wires. The various metal layers are interconnected by etching holes (called "vias") in the insulating material and then depositing tungsten in them with a CVD technique; this approach is still used in the fabrication of many memory chips such as dynamic random-access memory (DRAM), because the number of interconnect levels is small (currently no more than four).

More recently, as the number of interconnect levels for logic has substantially increased due to the large number of transistors that are now interconnected in a modern microprocessor, the timing delay in the wiring has become so significant as to prompt a change in wiring material (from aluminum to copper interconnect layer) and a change in dielectric material (from silicon dioxides to newer low-K insulators). This performance enhancement also comes at a reduced cost via damascene processing, which eliminates processing steps. As the number of interconnect levels increases, planarization of the previous layers is required to ensure a flat surface prior to subsequent lithography. Without it, the levels would become increasingly crooked, extending outside the depth of focus of available lithography, and thus interfering with the ability to pattern. CMP (chemical-mechanical planarization) is the primary processing method to achieve such planarization, although dry etch back is still sometimes employed when the number of interconnect levels is no more than three.

Wafer test

The highly serialized nature of wafer processing has increased the demand for metrology in between the various processing steps. For example, thin film metrology based on ellipsometry or reflectometry is used to tightly control the thickness of gate oxide, as well as the thickness, refractive index and extinction coefficient of photoresist and other coatings. Wafer test metrology equipment is used to verify that the wafers haven't been damaged by previous processing steps up until testing; if too many dies on one wafer have failed, the entire wafer is scrapped to avoid the costs of further processing. Virtual metrology has been used to predict wafer properties based on statistical methods without performing the physical measurement itself.

Device test

Once the front-end process has been completed, the semiconductor devices are subjected to a variety of electrical tests to determine if they function properly. The percent of devices on the wafer found to perform properly is referred to as the yield. Manufacturers are typically secretive about their yields, but it can be as low as 30%, meaning that only 30% of the chips on the wafer work as intended. Process variation is one among many reasons for low yield.

The number of defects is often but not necessarily proportional to device (die) size. As an example, In December 2019, TSMC announced an average yield of ~80%, with a peak yield per wafer of >90% for their 5nm test chips with a die size of 17.92 mm². The yield went down to 32.0% with an increase in die size to 100 mm². 

The fab tests the chips on the wafer with an electronic tester that presses tiny probes against the chip. The machine marks each bad chip with a drop of dye. Currently, electronic dye marking is possible if wafer test data (results) are logged into a central computer database and chips are "binned" (i.e. sorted into virtual bins) according to predetermined test limits such as maximum operating frequencies/clocks, number of working (fully functional) cores per chip, etc. The resulting binning data can be graphed, or logged, on a wafer map to trace manufacturing defects and mark bad chips. This map can also be used during wafer assembly and packaging. Binning allows chips that would otherwise be rejected to be reused in lower-tier products, as is the case with GPUs and CPUs, increasing device yield, specially since very few chips are fully functional (have all cores functioning correctly, for example). eFUSEs may be used to disconnect parts of chips such as cores, either because they didn't work as intended during binning, or as part of market segmentation (using the same chip for low, mid and high-end tiers). Chips may have spare parts to allow the chip to fully pass testing even if it has several non-working parts.

Chips are also tested again after packaging, as the bond wires may be missing, or analog performance may be altered by the package. This is referred to as the "final test". Chips may also be imaged using x-rays.

Usually, the fab charges for testing time, with prices in the order of cents per second. Testing times vary from a few milliseconds to a couple of seconds, and the test software is optimized for reduced testing time. Multiple chip (multi-site) testing is also possible because many testers have the resources to perform most or all of the tests in parallel.

Chips are often designed with "testability features" such as scan chains or a "built-in self-test" to speed testing and reduce testing costs. In certain designs that use specialized analog fab processes, wafers are also laser-trimmed during testing, in order to achieve tightly-distributed resistance values as specified by the design.

Good designs try to test and statistically manage corners (extremes of silicon behavior caused by a high operating temperature combined with the extremes of fab processing steps). Most designs cope with at least 64 corners.

Die preparation

Once tested, a wafer is typically reduced in thickness in a process also known as "backlap", "backfinish" or "wafer thinning" before the wafer is scored and then broken into individual dies, a process known as wafer dicing. Only the good, unmarked chips are packaged.

Packaging

Plastic or ceramic packaging involves mounting the die, connecting the die pads to the pins on the package, and sealing the die. Tiny bondwires are used to connect the pads to the pins. In the old days, wires were attached by hand, but now specialized machines perform the task. Traditionally, these wires have been composed of gold, leading to a lead frame (pronounced "leed frame") of solder-plated copper; lead is poisonous, so lead-free "lead frames" are now mandated by RoHS.

Chip scale package (CSP) is another packaging technology. A plastic dual in-line package, like most packages, is many times larger than the actual die hidden inside, whereas CSP chips are nearly the size of the die; a CSP can be constructed for each die before the wafer is diced.

The packaged chips are retested to ensure that they were not damaged during packaging and that the die-to-pin interconnect operation was performed correctly. A laser then etches the chip's name and numbers on the package.

Hazardous materials

Many toxic materials are used in the fabrication process. These include:

• poisonous elemental dopants, such as arsenic, antimony, and phosphorus.
• poisonous compounds, such as arsine, phosphine, and silane.
• highly reactive liquids, such as hydrogen peroxide, fuming nitric acid, sulfuric acid, and hydrofluoric acid.

It is vital that workers should not be directly exposed to these dangerous substances. The high degree of automation common in the IC fabrication industry helps to reduce the risks of exposure. Most fabrication facilities employ exhaust management systems, such as wet scrubbers, combustors, heated absorber cartridges, etc., to control the risk to workers and to the environment.

Field-effect transistor

From Wikipedia, the free encyclopedia

https://en.wikipedia.org/wiki/Field-effect_transistor 

 

Cross-sectional view of a field-effect transistor, showing source, gate and drain terminals

The field-effect transistor (FET) is a type of transistor which uses an electric field to control the flow of current. FETs are devices with three terminals: source, gate, and drain. FETs control the flow of current by the application of a voltage to the gate, which in turn alters the conductivity between the drain and source.

FETs are also known as unipolar transistors since they involve single-carrier-type operation. That is, FETs use either electrons or holes as charge carriers in their operation, but not both. Many different types of field effect transistors exist. Field effect transistors generally display very high input impedance at low frequencies. The most widely used field-effect transistor is the MOSFET (metal-oxide-semiconductor field-effect transistor).

History

Julius Edgar Lilienfeld proposed the concept of a field-effect transistor in 1925.

The concept of a field-effect transistor (FET) was first patented by Austro-Hungarian physicist Julius Edgar Lilienfeld in 1925 and by Oskar Heil in 1934, but they were unable to build a working practical semiconducting device based on the concept. The transistor effect was later observed and explained by John Bardeen and Walter Houser Brattain while working under William Shockley at Bell Labs in 1947, shortly after the 17-year patent expired. Shockley initially attempted to build a working FET, by trying to modulate the conductivity of a semiconductor, but was unsuccessful, mainly due to problems with the surface states, the dangling bond, and the germanium and copper compound materials. In the course of trying to understand the mysterious reasons behind their failure to build a working FET, this led to Bardeen and Brattain instead building a point-contact transistor in 1947, which was followed by Shockley's bipolar junction transistor in 1948.

The first FET device to be successfully built was the junction field-effect transistor (JFET). A JFET was first patented by Heinrich Welker in 1945. The static induction transistor (SIT), a type of JFET with a short channel, was invented by Japanese engineers Jun-ichi Nishizawa and Y. Watanabe in 1950. Following Shockley's theoretical treatment on the JFET in 1952, a working practical JFET was built by George F. Dacey and Ian M. Ross in 1953. However, the JFET still had issues affecting junction transistors in general. Junction transistors were relatively bulky devices that were difficult to manufacture on a mass-production basis, which limited them to a number of specialised applications. The insulated-gate field-effect transistor (IGFET) was theorized as a potential alternative to junction transistors, but researchers were unable to build working IGFETs, largely due to the troublesome surface state barrier that prevented the external electric field from penetrating into the material. By the mid-1950s, researchers had largely given up on the FET concept, and instead focused on bipolar junction transistor (BJT) technology.

The foundations of MOSFET technology was laid down by the work of William Shockley, John Bardeen and Walter Brattain. Shockley independently envisioned the FET concept in 1945, but he was unable to build a working device. The next year Bardeen explained his failure in terms of surface states. Bardeen applied the theory of surface states on semiconductors (previous work on surface states was done by Shockley in 1939 and Igor Tamm in 1932) and realized that the external field was blocked at the surface because of extra electrons which are drawn to the semiconductor surface. Electrons become trapped in those localized states forming an inversion layer. Bardeen's hypothesis marked the birth of surface physics. Bardeen then decided to make use of an inversion layer and use it instead of a very thin layer of semiconductor which Shockley envisioned in his FET designs. Based on his theory, in 1948 Bardeen patented the progenitor of MOSFET, an insulated-gate FET (IGFET) with an inversion layer. The inversion layer confines the flow of minority carriers, increases modulation and conductivity, although its electron transport depends on gate's insulator or quality of oxide if used as an insulator, deposited above the inversion layer. Bardeen's patent as well as the concept of inversion layer forms the basis of CMOS technology today. In 1976 Shockley has described Bardeen's surface state hypothesis "as one of the most significant research ideas in the semiconductor program".

After Bardeen's surface state theory the trio tried to overcome the effect of surface states. In late 1947, Robert Gibney and Brattain suggested the use of electrolyte placed between metal and semiconductor to overcome the effects of surface states. Their FET device worked, but amplification was poor. Bardeen went further and suggested to rather focus on the conductivity of the inversion layer. Further experiments led them to replace electrolyte with a solid oxide layer in the hope of getting better results. Their goal was to penetrate the oxide layer and get to the inversion layer. However, Bardeen suggested they switch from silicon to germanium and in the process their oxide got inadvertently washed off. They stumbled upon completely different transistor, the point-contact transistor. Lillian Hoddeson argues that "had Brattain and Bardeen been working with silicon instead of germanium they would have stumbled across a successful field effect transistor".

By the end the of the first half of 1950s, following theoretical and experimental work of Bardeen, Brattain, Kingston, Morrison and others, it became more clear that there were two types of surface states. Fast surface states were found to be associated with the bulk and a semiconductor/oxide interface. Slow surface states were found to be associated with the oxide layer because of adsorption of atoms, molecules and ions by the oxide from the ambient. The latter were found to be much more numerous and to have much longer relaxation times. At the time Philo Farnsworth and others came up with various methods of producing atomically clean semiconductor surfaces.

In 1955, Carl Frosch and Lincoln Derrick accidentally covered the surface of silicon wafer with a layer of silicon dioxide. They showed that oxide layer prevented certain dopants into the silicon wafer, while allowing for others, thus discovering the passivating effect of oxidation on the semiconductor surface. Their further work demonstrated how to etch small openings in the oxide layer to diffuse dopants into selected areas of the silicon wafer. In 1957, they published a research paper and patented their technique summarizing their work. The technique they developed is known as oxide diffusion masking, which would later be used in the fabrication of MOSFET devices. At Bell Labs, the importance of Frosch's technique was immediately realized. Results of their work circulated around Bell Labs in the form of BTL memos before being published in 1957. At Shockley Semiconductor, Shockley had circulated the preprint of their article in December 1956 to all his senior stuff, including Jean Hoerni.

In 1955, Ian Munro Ross filed a patent for a FeFET or MFSFET. Its structure was like that of a modern inversion channel MOSFET, but ferroelectric material was used as a dielectric/insulator instead of oxide. He envisioned it as a form of memory, years before the floating gate MOSFET. In February 1957, John Wallmark filed a patent for FET in which germanium monoxide was used as a gate dielectric, but he didn't pursue the idea. In his other patent filed the same year he described a double gate FET. In March 1957, in his laboratory notebook, Ernesto Labate, a research scientist at Bell Labs, conceived of a device similar to the later proposed MOSFET, although Labate's device didn't explicitly use silicon dioxide as an insulator.

Metal-oxide-semiconductor FET (MOSFET)

Mohamed Atalla (left) and Dawon Kahng (right) invented the MOSFET (MOS field-effect transistor) in 1959.

A breakthrough in FET research came with the work of Egyptian engineer Mohamed Atalla in the late 1950s. In 1958 he presented experimental work which showed that growing thin silicon oxide on clean silicon surface leads to neutralization of surface states. This is known as surface passivation, a method that became critical to the semiconductor industry as it made mass-production of silicon integrated circuits possible.

The metal–oxide–semiconductor field-effect transistor (MOSFET) was then invented by Mohamed Atalla and Dawon Kahng in 1959. The MOSFET largely superseded both the bipolar transistor and the JFET, and had a profound effect on digital electronic development. With its high scalability, and much lower power consumption and higher density than bipolar junction transistors, the MOSFET made it possible to build high-density integrated circuits. The MOSFET is also capable of handling higher power than the JFET. The MOSFET was the first truly compact transistor that could be miniaturised and mass-produced for a wide range of uses. The MOSFET thus became the most common type of transistor in computers, electronics, and communications technology (such as smartphones). The US Patent and Trademark Office calls it a "groundbreaking invention that transformed life and culture around the world".

CMOS (complementary MOS), a semiconductor device fabrication process for MOSFETs, was developed by Chih-Tang Sah and Frank Wanlass at Fairchild Semiconductor in 1963. The first report of a floating-gate MOSFET was made by Dawon Kahng and Simon Sze in 1967. A double-gate MOSFET was first demonstrated in 1984 by Electrotechnical Laboratory researchers Toshihiro Sekigawa and Yutaka Hayashi. FinFET (fin field-effect transistor), a type of 3D non-planar multi-gate MOSFET, originated from the research of Digh Hisamoto and his team at Hitachi Central Research Laboratory in 1989.

Basic information

FETs can be majority-charge-carrier devices, in which the current is carried predominantly by majority carriers, or minority-charge-carrier devices, in which the current is mainly due to a flow of minority carriers. The device consists of an active channel through which charge carriers, electrons or holes, flow from the source to the drain. Source and drain terminal conductors are connected to the semiconductor through ohmic contacts. The conductivity of the channel is a function of the potential applied across the gate and source terminals.

The FET's three terminals are:

1. source (S), through which the carriers enter the channel. Conventionally, current entering the channel at S is designated by I_S.
2. drain (D), through which the carriers leave the channel. Conventionally, current entering the channel at D is designated by I_D. Drain-to-source voltage is V_DS.
3. gate (G), the terminal that modulates the channel conductivity. By applying voltage to G, one can control I_D.

More about terminals

Cross section of an n-type MOSFET

All FETs have source, drain, and gate terminals that correspond roughly to the emitter, collector, and base of BJTs. Most FETs have a fourth terminal called the body, base, bulk, or substrate. This fourth terminal serves to bias the transistor into operation; it is rare to make non-trivial use of the body terminal in circuit designs, but its presence is important when setting up the physical layout of an integrated circuit. The size of the gate, length L in the diagram, is the distance between source and drain. The width is the extension of the transistor, in the direction perpendicular to the cross section in the diagram (i.e., into/out of the screen). Typically the width is much larger than the length of the gate. A gate length of 1 µm limits the upper frequency to about 5 GHz, 0.2 µm to about 30 GHz.

The names of the terminals refer to their functions. The gate terminal may be thought of as controlling the opening and closing of a physical gate. This gate permits electrons to flow through or blocks their passage by creating or eliminating a channel between the source and drain. Electron-flow from the source terminal towards the drain terminal is influenced by an applied voltage. The body simply refers to the bulk of the semiconductor in which the gate, source and drain lie. Usually the body terminal is connected to the highest or lowest voltage within the circuit, depending on the type of the FET. The body terminal and the source terminal are sometimes connected together since the source is often connected to the highest or lowest voltage within the circuit, although there are several uses of FETs which do not have such a configuration, such as transmission gates and cascode circuits.

Effect of gate voltage on current

I–V characteristics and output plot of a JFET n-channel transistor.

 

Simulation result for right side: formation of inversion channel (electron density) and left side: current-gate voltage curve (transfer characteristics) in an n-channel nanowire MOSFET. Note that the threshold voltage for this device lies around 0.45 V.

 

FET conventional symbol types

The FET controls the flow of electrons (or electron holes) from the source to drain by affecting the size and shape of a "conductive channel" created and influenced by voltage (or lack of voltage) applied across the gate and source terminals. (For simplicity, this discussion assumes that the body and source are connected.) This conductive channel is the "stream" through which electrons flow from source to drain.

n-channel FET

In an n-channel "depletion-mode" device, a negative gate-to-source voltage causes a depletion region to expand in width and encroach on the channel from the sides, narrowing the channel. If the active region expands to completely close the channel, the resistance of the channel from source to drain becomes large, and the FET is effectively turned off like a switch (see right figure, when there is very small current). This is called "pinch-off", and the voltage at which it occurs is called the "pinch-off voltage". Conversely, a positive gate-to-source voltage increases the channel size and allows electrons to flow easily (see right figure, when there is a conduction channel and current is large).

In an n-channel "enhancement-mode" device, a conductive channel does not exist naturally within the transistor, and a positive gate-to-source voltage is necessary to create one. The positive voltage attracts free-floating electrons within the body towards the gate, forming a conductive channel. But first, enough electrons must be attracted near the gate to counter the dopant ions added to the body of the FET; this forms a region with no mobile carriers called a depletion region, and the voltage at which this occurs is referred to as the threshold voltage of the FET. Further gate-to-source voltage increase will attract even more electrons towards the gate which are able to create a conductive channel from source to drain; this process is called inversion.

p-channel FET

In a p-channel "depletion-mode" device, a positive voltage from gate to body widens the depletion layer by forcing electrons to the gate-insulator/semiconductor interface, leaving exposed a carrier-free region of immobile, positively charged acceptor ions.

Conversely, in a p-channel "enhancement-mode" device, a conductive region does not exist and negative voltage must be used to generate a conduction channel.

Effect of drain-to-source voltage on channel

For either enhancement- or depletion-mode devices, at drain-to-source voltages much less than gate-to-source voltages, changing the gate voltage will alter the channel resistance, and drain current will be proportional to drain voltage (referenced to source voltage). In this mode the FET operates like a variable resistor and the FET is said to be operating in a linear mode or ohmic mode.

If drain-to-source voltage is increased, this creates a significant asymmetrical change in the shape of the channel due to a gradient of voltage potential from source to drain. The shape of the inversion region becomes "pinched-off" near the drain end of the channel. If drain-to-source voltage is increased further, the pinch-off point of the channel begins to move away from the drain towards the source. The FET is said to be in saturation mode; although some authors refer to it as active mode, for a better analogy with bipolar transistor operating regions. The saturation mode, or the region between ohmic and saturation, is used when amplification is needed. The in-between region is sometimes considered to be part of the ohmic or linear region, even where drain current is not approximately linear with drain voltage.

Even though the conductive channel formed by gate-to-source voltage no longer connects source to drain during saturation mode, carriers are not blocked from flowing. Considering again an n-channel enhancement-mode device, a depletion region exists in the p-type body, surrounding the conductive channel and drain and source regions. The electrons which comprise the channel are free to move out of the channel through the depletion region if attracted to the drain by drain-to-source voltage. The depletion region is free of carriers and has a resistance similar to silicon. Any increase of the drain-to-source voltage will increase the distance from drain to the pinch-off point, increasing the resistance of the depletion region in proportion to the drain-to-source voltage applied. This proportional change causes the drain-to-source current to remain relatively fixed, independent of changes to the drain-to-source voltage, quite unlike its ohmic behavior in the linear mode of operation. Thus, in saturation mode, the FET behaves as a constant-current source rather than as a resistor, and can effectively be used as a voltage amplifier. In this case, the gate-to-source voltage determines the level of constant current through the channel.

Composition

FETs can be constructed from various semiconductors—silicon is by far the most common. Most FETs are made by using conventional bulk semiconductor processing techniques, using a single crystal semiconductor wafer as the active region, or channel.

Among the more unusual body materials are amorphous silicon, polycrystalline silicon or other amorphous semiconductors in thin-film transistors or organic field-effect transistors (OFETs) that are based on organic semiconductors; often, OFET gate insulators and electrodes are made of organic materials, as well. Such FETs are manufactured using a variety of materials such as silicon carbide (SiC), gallium arsenide (GaAs), gallium nitride (GaN), and indium gallium arsenide (InGaAs).

In June 2011, IBM announced that it had successfully used graphene-based FETs in an integrated circuit. These transistors are capable of about 2.23 GHz cutoff frequency, much higher than standard silicon FETs.

Types

Depletion-type FETs under typical voltages: JFET, poly-silicon MOSFET, double-gate MOSFET, metal-gate MOSFET, MESFET.

  Depletion

  Electrons

  Holes

  Metal

  Insulator

Top: source, bottom: drain, left: gate, right: bulk. Voltages that lead to channel formation are not shown.

The channel of a FET is doped to produce either an n-type semiconductor or a p-type semiconductor. The drain and source may be doped of opposite type to the channel, in the case of enhancement mode FETs, or doped of similar type to the channel as in depletion mode FETs. Field-effect transistors are also distinguished by the method of insulation between channel and gate. Types of FETs include:

• The MOSFET (metal–oxide–semiconductor field-effect transistor) utilizes an insulator (typically SiO₂) between the gate and the body. This is by far the most common type of FET.
  • The DGMOSFET (dual-gate MOSFET) or DGMOS, a MOSFET with two insulated gates.
  • The IGBT (insulated-gate bipolar transistor) is a device for power control. It has a structure akin to a MOSFET coupled with a bipolar-like main conduction channel. These are commonly used for the 200–3000 V drain-to-source voltage range of operation. Power MOSFETs are still the device of choice for drain-to-source voltages of 1 to 200 V.
  • The MNOS (metal–nitride–oxide–semiconductor transistor) utilizes a nitride-oxide layer insulator between the gate and the body.
  • The ISFET (ion-sensitive field-effect transistor) can be used to measure ion concentrations in a solution; when the ion concentration (such as H⁺, see pH electrode) changes, the current through the transistor will change accordingly.
  • The BioFET (Biologically sensitive field-effect transistor) is a class of sensors/biosensors based on ISFET technology which are utilized to detect charged molecules; when a charged molecule is present, changes in the electrostatic field at the BioFET surface result in a measurable change in current through the transistor. These include enzyme modified FETs (EnFETs), immunologically modified FETs (ImmunoFETs), gene-modified FETs (GenFETs), DNAFETs, cell-based BioFETs (CPFETs), beetle/chip FETs (BeetleFETs), and FETs based on ion-channels/protein binding.
  • The DNAFET (DNA field-effect transistor) is a specialized FET that acts as a biosensor, by using a gate made of single-strand DNA molecules to detect matching DNA strands.
• The JFET (junction field-effect transistor) uses a reverse biased p–n junction to separate the gate from the body.
  • The static induction transistor (SIT) is a type of JFET with a short channel.
• The DEPFET is a FET formed in a fully depleted substrate and acts as a sensor, amplifier and memory node at the same time. It can be used as an image (photon) sensor.
• The FREDFET (fast-reverse or fast-recovery epitaxial diode FET) is a specialized FET designed to provide a very fast recovery (turn-off) of the body diode, making it convenient for driving inductive loads such as electric motors, especially medium-powered brushless DC motors.
• The HIGFET (heterostructure insulated-gate field-effect transistor) is now used mainly in research.
• The MODFET (modulation-doped field-effect transistor) is a high-electron-mobility transistor using a quantum well structure formed by graded doping of the active region.
• The TFET (tunnel field-effect transistor) is based on band-to-band tunneling.
• The HEMT (high-electron-mobility transistor), also called a HFET (heterostructure FET), can be made using bandgap engineering in a ternary semiconductor such as AlGaAs. The fully depleted wide-band-gap material forms the isolation between gate and body.
• The MESFET (metal–semiconductor field-effect transistor) substitutes the p–n junction of the JFET with a Schottky barrier; and is used in GaAs and other III-V semiconductor materials.
• The NOMFET is a nanoparticle organic memory field-effect transistor.
• The GNRFET (graphene nanoribbon field-effect transistor) uses a graphene nanoribbon for its channel.
• The VeSFET (vertical-slit field-effect transistor) is a square-shaped junctionless FET with a narrow slit connecting the source and drain at opposite corners. Two gates occupy the other corners, and control the current through the slit.
• The CNTFET (carbon nanotube field-effect transistor).
• The OFET (organic field-effect transistor) uses an organic semiconductor in its channel.
• The QFET (quantum field effect transistor) takes advantage of quantum tunneling to greatly increase the speed of transistor operation by eliminating the traditional transistor's area of electron conduction.
• The SB-FET (Schottky-barrier field-effect transistor) is a field-effect transistor with metallic source and drain contact electrodes, which create Schottky barriers at both the source-channel and drain-channel interfaces.
• The GFET is a highly sensitive graphene-based field effect transistor used as biosensors and chemical sensors. Due to the 2 dimensional structure of graphene, along with its physical properties, GFETs offer increased sensitivity, and reduced instances of 'false positives' in sensing applications
• The Fe FET uses a ferroelectric between the gate, allowing the transistor to retain its state in the absence of bias - such devices may have application as non-volatile memory.

Advantages

The FET has high gate-to-drain current resistance, on the order of 100 MΩ or more, providing a high degree of isolation between control and flow. Because base current noise will increase with shaping time, a FET typically produces less noise than a bipolar junction transistor (BJT), and is found in noise-sensitive electronics such as tuners and low-noise amplifiers for VHF and satellite receivers. It is relatively immune to radiation. It exhibits no offset voltage at zero drain current and makes an excellent signal chopper. It typically has better thermal stability than a BJT. Because they are controlled by gate charge, once the gate is closed or open, there is no additional power draw, as there would be with a bipolar junction transistor or with non-latching relays in some states. This allows extremely low-power switching, which in turn allows greater miniaturization of circuits because heat dissipation needs are reduced compared to other types of switches.

Disadvantages

A field-effect transistor has a relatively low gain–bandwidth product compared to a BJT. The MOSFET is very susceptible to overload voltages, thus requiring special handling during installation. The fragile insulating layer of the MOSFET between the gate and channel makes it vulnerable to electrostatic discharge or changes to threshold voltage during handling. This is not usually a problem after the device has been installed in a properly designed circuit.

FETs often have a very low "on" resistance and have a high "off" resistance. However, the intermediate resistances are significant, and so FETs can dissipate large amounts of power while switching. Thus efficiency can put a premium on switching quickly, but this can cause transients that can excite stray inductances and generate significant voltages that can couple to the gate and cause unintentional switching. FET circuits can therefore require very careful layout and can involve trades between switching speed and power dissipation. There is also a trade-off between voltage rating and "on" resistance, so high-voltage FETs have a relatively high "on" resistance and hence conduction losses.

Failure modes

FETs are relatively robust, especially when operated within the temperature and electrical limitations defined by the manufacturer (proper derating). However, modern FET devices can often incorporate a body diode. If the characteristics of the body diode are not taken into consideration, the FET can experience slow body diode behavior, where a parasitic transistor will turn on and allow high current to be drawn from drain to source when the FET is off.

Uses

The most commonly used FET is the MOSFET. The CMOS (complementary metal oxide semiconductor) process technology is the basis for modern digital integrated circuits. This process technology uses an arrangement where the (usually "enhancement-mode") p-channel MOSFET and n-channel MOSFET are connected in series such that when one is on, the other is off.

In FETs, electrons can flow in either direction through the channel when operated in the linear mode. The naming convention of drain terminal and source terminal is somewhat arbitrary, as the devices are typically (but not always) built symmetrical from source to drain. This makes FETs suitable for switching analog signals between paths (multiplexing). With this concept, one can construct a solid-state mixing board, for example. FET is commonly used as an amplifier. For example, due to its large input resistance and low output resistance, it is effective as a buffer in common-drain (source follower) configuration.

IGBTs are used in switching internal combustion engine ignition coils, where fast switching and voltage blocking capabilities are important.

Source-gated transistor

Source-gated transistors are more robust to manufacturing and environmental issues in large-area electronics such as display screens, but are slower in operation than FETs.