Gay–straight alliance

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https://en.wikipedia.org/wiki/Gay-straight_alliance 

 

Gay–Straight Alliance

Abbreviation	GSA
Nickname	Gender–Sexuality Alliance
Type	Student club
Legal status	In the US, the right of students to form a GSA at school is protected by the Constitution and by the judiciary.
Purpose	Provide a supportive environment for LGBT youth and straight allies
Location	United States, Canada, the United Kingdom, New Zealand, Mexico, Europe, India, Hong Kong and Australia
Parent organization	GLSEN

A Gay–Straight Alliance, Gender-Sexuality Alliance (GSA) or Queer–Straight Alliance (QSA) is a student-led or community-based organisation, found in middle schools, high schools, colleges, and universities. These are primarily in the United States and Canada. Gay–straight alliance is intended to provide a safe and supportive environment for lesbian, gay, bisexual, transgender, and all (LGBTQ+) children, teenagers, and youth as well as their cisgender heterosexual allies. In middle schools and high schools, GSAs are overseen by a responsible teacher. The first GSAs were established in the 1980s. Scientific studies show that GSAs have positive academic, health, and social impacts on schoolchildren of a minority sexual orientation and/or gender identity. Numerous judicial decisions in United States federal and state court jurisdictions have upheld the establishment of GSAs in schools, and the right to use that name for them.

Terminology

I hella love the GSA

• ally – In the context of the founding in 1988, an ally is a cisgender, heterosexual person who supports equal rights for gay people and challenges homophobia. The meaning later expanded to include rights for all LGBTQ+ individuals, orientations, and gender identities.
• Gay–Straight Alliance – name proposed by Meredith Sterling for the original club in 1988. Sometimes with slash instead of dash.
• Gay Straight Alliance – in title case, and without hyphen on the founder website.
• gay–straight alliances – in lowercase, a generalized term for any club of this nature
• Gay–Straight Alliance Network (GSA Network) – an organization founded in California in 1998 to support and promote GSAs.
• gender–sexuality alliance – updated name for gay–straight alliance, the old name appearing "too binary" for a later generation
• Genders & Sexualities Alliance Network – new name (2016) for the Gay–Straight Alliance Network
• Gay, Lesbian & Straight Education Network (GLSEN) – organization founded in 1990 in Boston
• GSA – originally, designated a gay–straight alliance club, later, a gender–sexuality alliance club
• QSA – is used for more inclusive use, as the community is more than 'Gay', the use of Queer being used allows other students that may fit the queer definition, like transgender or bisexual students, to be represented in these support groups.
• Sexuality And Gender Acceptance/Awareness/Alliance/Association (SAGA) – unspecific general term, used as an alternative to both LGBT and GSA.

History

Gay–Straight Alliance at Concord

The first gay–straight alliance was formed in November 1988 at Concord Academy in Concord, Massachusetts, when Kevin Jennings, a history teacher at the school who had just come out as gay, was approached by Meredith Sterling, a student at the school who was straight, but was upset by the treatment of gay students and others. Jennings recruited some other teachers at the school, thus forming the first gay–straight alliance. One of the first to join was Sterling's classmate S. Bear Bergman. Jennings credits students for both the establishment of the club, as well as for setting the agenda of struggling against homophobia, and for changes to CA's nondiscrimination policy. Jennings would go on to co-found the Gay, Lesbian & Straight Education Network (GLSEN) in Boston in 1990.

According to a thirty-year retrospective about the history of the group, Concord Academy reported in 2018 that students at the academy had renamed the group "a few years ago" to "Gender Sexuality Alliance". Faculty mentor Nancy Boutilier said, "That gay–straight language was really important at the time. Times change, though. To students today, that sounds so binary."

GSA at Phillips Academy

A few months after Concord started the first Gay Straight Alliance club, another Massachusetts preparatory school north of Boston, Phillips Academy, started one of their own. It began with a meeting called by Phillips student Sharon Tentarelli for February 7, 1989, with little advance notice. A dozen people attended, including a mix of student, teachers, and staff. This was the second such group, after Concord Academy. The group was well-received, and some staff and faculty became supporters, both gay, and straight. Athletic director Kathy Henderson was one of the supporters, and she later went on to co-found the GLSEN two years later, along with Kevin Jennings of Concord Academy.

GSA Network

The GSA Network is an LGBT rights organization was founded in 1998 by Carolyn Laub to empower youth activists to start GSA clubs in their respective schools to motivate and inspire fellow students to fight against homophobia and transphobia. Laub initially started working with this movement in 40 GSA clubs in the San Francisco Bay area during 1988–99 and then gradually expanded to other cities and states. By 2001, The GSA Network became a statewide organization having branches in other schools in different parts of the state. In the year 2005, it began operating programs nationally. The year 2008 saw the GSA network become incorporated as its own independent 501(c)3 non-profit organization. Prior to that, it was a fiscally sponsored project of The Tides Center. In 2015, the network hired two long time staff to serve as Co-Executive Directors to replace outgoing founder and Executive Director Carolyn Laub. In 2016, the Gay–Straight Alliance Network formally changed its name to Genders & Sexualities Alliance Network and continues to network organizations representing over 4000 GSA clubs across the nation.

The GSA Network organization is based in Oakland and has regional offices in Los Angeles, Fresno, Chicago, and Atlanta.

Goal

The goal of most gay–straight alliances is to make their school community safe, facilitate activism on campus, and create a welcoming environment for LGBT students. They are part of the LGBT student movement and participate in national campaigns to raise awareness, such as the Day of Silence, National Coming Out Day, No Name Calling Week, Transgender Day of Remembrance, Harvey Milk Day, GSA day or locally organized campaigns, such as Take It Back: Anti-Slur Campaign, Beyond the Binary, LGBTQ-Inclusive Curriculum and others. Many GSAs work with local chapters of the Gay, Lesbian and Straight Education Network (GLSEN) or Gay–Straight Alliance Network, a national organization supporting youth leadership. The registered number of GSAs with GLSEN is over 4,000, as of 2008. In California, there are over 900 GSAs registered with GSA Network, representing over half of California's high schools. Over half the states in the United States have one or more statewide groups that work with GSAs. Many of these state based groups and local chapters of GLSEN participate in the National Association of GSA Networks. GSA Networks have been formed to help local area students to network and connect to local resources, provide training for youth leaders, and sponsor local GSA efforts.

The inclusion of cisgender heterosexual allies in the missions of these groups "is an important distinguishing factor from early support groups for LGBT teens, and recognizes the need for a comprehensive approach to youth safety," and attempts to build a network of support for non-heterosexual and transgender teens, as well as raising awareness of homophobia and heterosexism.

Impact

Outcomes

Social

LGBT students routinely experience harassment in their schools however, GSAs and other support clubs have been found to provide social support for LGBT students. Students have reported hearing homophobic remarks from both students and instructors in their schools. In addition, the more harassment students reported, the more likely the student also reported higher levels of depression and lower self-esteem. However, LGBT students attending a school with an active support club reported hearing less homophobic expressions and experienced less victimization than LGBT students attending a school without a GSA or support club. In addition, LGBT students with a GSA in their high school reported more positive outcomes when it came to high school belonging and school victimization.

In addition to the mere presence of a GSA on campus, level of participation in a GSA has also been linked to the amount of social support reported by LGBT students. A 2011 study by Toomey, Ryan, Diaz and Russell (2011) found that the presence of a GSA, participation in a GSA, and perceived effectiveness of a GSA were each individually associated with youth's well-being. In certain cases, research showed these three factors protected youth's well-being against victimization. Furthermore, youths who participated in a GSA reported lower levels of depression and higher self-esteem.

GSAs are important not only at the individual level, but also to promote the education of LGBT issues to school populations. GSA's have been found to promote social activism. Researchers have argued that GSAs are a grassroots student initiated form of activism. The same researchers claimed that GSAs are important to challenge the status quo, confront discrimination, and reconceptualize gender.

Academic

LGBT youths in schools across the US are subject to serious obstacles that may impact their ability to perform in school. A 2011 study found that two thirds of LGBT students reported feeling unsafe at school. Some students felt so unsafe that they reported missing school due to safety concerns. The same study found that the GPA of LGBT children was, on average, half a grade lower than straight. This may be an indicator that LGBT youth face different barriers to education than straight youth.

LGBT youth's school experience may impact their life decisions. LGBT youth in high school were less likely to report that they wanted to pursue further education than straight youth. These findings suggest that LGBT youths' negative experiences in primary education relate to their decision not to continue on in the education system. This then robs LGBT youth of all of the opportunities that advanced education offers.

However, an active GSA on a high school campus has been associated with better academic outcomes for LGBT students. LGBT youth attending schools with an active GSA were less likely to report feeling unsafe at school and were less likely to miss school due to a threat to their safety. Additionally, LGBT youths who had an active GSA at their high school reported higher educational attainment than LGBT youth who did not have a GSA on their high school campus.

Health

GSAs/QSAs are associated with better mental health outcomes, such as less depression less general psychological distress and higher self-esteem than students without a GSA at their high school. The positive impacts of GSAs/QSAs in students' lives include: increase in school attendance and attachment to the school, sense of empowerment and hope, new friendships, reduction in stress and isolation, increase in confidence and sense of pride. Students in schools that had an active GSA also reported less truancy). LGBT students with a support club in their school also reported lower levels of victimization and suicide attempts in comparison to schools without a support group).

GSAs have also been associated with other reduced health risk factors. LGBT students with a GSA in their high school reported more positive outcomes when it came to alcohol use and problems related to alcohol use. LGBT students with support groups in their schools reported half as much dating violence and less casual sex. Students with an active GSA in their high school were also less likely to be threatened or injured at school in comparison to students without an active GSA.

Impact on students

GSAs are associated with benefits for LGBT students while they are attending school and beyond. The next important step is to understand why GSAs are associated with these benefits. One qualitative study found that the most beneficial aspect of a GSA was that it provides direct support to LGBTQ members and helps create a support network for LGBT students by connecting them. Another qualitative study found that GSAs were beneficial to LGBTQ students because they act as a protective factor for LGBT students' educational and social experience in school. The study further explained that GSAs provided LGBT students with a sense of identity within their school, improved their self-esteem, and even provided students with courage and support to come out to their families and peers.

One study investigated some of the possible factors within GSAs to discover which specific components of GSAs were associated with which beneficial outcomes. This study found that when GSA advisors served for longer periods of time, students had better health outcomes. In addition, LGBT students who perceived they had more control over their GSA experience and LGBT students who perceived their school to be more supportive had healthier outcomes. In addition, this study reported that "students level of GSA advocacy also predicted students' sense of life purpose."

Impact after high school

The relationship between having a GSA in a high school and attitudes towards LGBT individuals does not end after high school. The mere presence of a GSA, whether or not students participated in said GSA, is related to students' attitudes toward LGBT people beyond their time in their high school. University students who reported having a GSA in their high school were more likely to report positive attitudes towards LGBT individuals while attending their university. This was true for all students except students whom were raised in the southern U.S. where having a GSA in one's high school actually correlated with less positive attitudes toward LGBT individuals.

Impact summary

GSAs are associated with positive social academic and health outcomes for LGBT students. The relationship between having a GSA in one's high school and certain positive social outcomes is known to last beyond high school, however little beyond that is known about the long lasting associations with high school GSAs. Further research should be conducted on the lasting effects if GSAs for LGBT individuals. Researchers have also claimed that GSAs are important not only to LGBT students, but also to change the school climate as a whole to be more informed and respectful of LGBT issues. It has also been claimed that GSAs are important to get students involved in social activism. Researchers should investigate the relationship between having a GSA in a high school the school's social climate. Due to the positive associations between GSAs and student outcomes, school faculty including school psychologists and counselors should become social justice advocates for LGBTQ students by supporting GSAs on their campuses.

Accomplishments

The various accomplishments since the founding of the GSAs include:

• GSAs have played a great leadership role in the grassroots by organizing the passage of many ground-breaking, statewide legislations, like the AB 537: The California Student Safety and Violence Prevention Act of 2000 which prohibits discrimination on the basis of sexual orientation and gender identity.
• It has achieved a critical victory as the plaintiff in the first lawsuit filed under AB 537; which was a three-year settlement agreement which required the Visalia schools to enact sweeping reforms including mandatory teacher and student trainings that would be supportive to LGBT students.
• It also helped to pass 11 key laws to protect LGBT youth and create safer school environment.
• They also launched the National Association of GSA Networks in 2005 to unite statewide organizations to support GSAs and to accelerate the growth and impact of the GSA movement nationwide. To date, there are 40 states which have joined the National Association in the United States of America alone.

History in the United States

Described as "perhaps the most important precursor of the GSA movement," Los Angeles' Project 10 is seen as the start of the GSA movement. Founded in 1984, Project 10 was widely recognised as the first organised effort to provide support for LGBTQ youth in schools across the United States. The majority of its facilitators were heterosexual, and was named after the commonly-held statistic that 10 per cent of the adult male population is "exclusively homosexual". Project 10 focused on issues such as substance use, and discussing issues of high-risk sexual behavior.

The first GSA was started in 1988, in Concord, Massachusetts at Concord Academy by Kevin Jennings. The first public school gay–straight alliance was started at Newton South High School (Newton, Massachusetts) by teacher Robert Parlin. GSAs made headlines in 1999 with the Federal Court ruling in Utah–East High Gay/Straight Alliance v. Board of Education of Salt Lake City School District. This ruling found that denying access to a school-based gay–straight alliance was a violation of the Federal Equal Access Act giving students the right to use facilities for extra curricular activities at any school that receives public funding—regardless of private standing or religious affiliation.

On January 24, 2012, the United States Secretary of Education, Arne Duncan, released a video on YouTube commemorating GSA Day and endorsing GSA clubs in schools.

Inclusivity

Approximately 28 per cent of participants at GSA Network identify as heterosexual.

Opposition

Some students face opposition from school administrations, elected school boards, or local communities in starting a school GSA.

In 2015, students at Brandon High School in Rankin County, Mississippi, attempted to start a GSA, but the school board met and publicly stated they wanted to prevent the formation of "gay clubs" in the school district. They then created a policy requiring parents to provide written permission before a student can join any club. Students then protested with support from the ACLU.

Students at West Carteret High School in Morehead City, North Carolina tried to start a GSA but the Carteret County Board of Education turned it down. In 1999, the Orange Unified School District in Orange County, California moved to prohibit the formation of a GSA at El Modena High School. The students then sued the school board, claiming that their rights under the First Amendment and the 1984 Equal Access Act had been violated. In the first-ever ruling of its kind, Judge David O. Carter of the United States District Court for the Central District of California issued a preliminary injunction ordering the school to allow the GSA to meet.

The right of students to establish a GSA at school is guaranteed by both the First Amendment to the United States Constitution (with regard to every level of schooling) and the federal Equal Access Act (with regard to secondary schools as long as other student clubs are allowed, with the definition of secondary school for purposes of the federal law including middle schools and high schools).

GSAs cannot be banned if other non-curricular student clubs are allowed to exist at the school. The Federal Equal Access Act and the First Amendment of the US Constitution establish the requirement of equal treatment for all non-curriculum related clubs regardless of the content of speech at the club meetings.

— GSA Network

Case law

In the United States, the right of students to establish a GSA at school is guaranteed by both the First Amendment to the United States Constitution (with regard to every level of schooling) and the federal Equal Access Act (with regard to secondary schools where other student clubs are allowed, with the definition of secondary school for purposes of the federal law including middle schools and high schools). Since 1998, there have been at least 17 federal court cases in which high school and middle school students have conclusively prevailed in defending the free exercise of their civil rights on this issue, with federal courts consistently ruling that students have both a right to establish a GSA at school and to use the name Gay–Straight Alliance instead of an alternative name. In 2000, the United States District Court for the Central District of California ruled in favor of high school students whose attempt to form a GSA had been blocked by the school board, in the case of Colin v. Orange Unified School District. In 2009, the United States District Court for the Middle District of Florida ruled in favor of high school students whose attempt to form a GSA had been blocked by the school board, in the case of Gay–Straight Alliance of Yulee High School v. School Board of Nassau County, with the federal court also ruling that the school must allow the students to use the name Gay–Straight Alliance instead of an alternative name that excludes the term Gay. In 2016, the United States Court of Appeals for the Eleventh Circuit unanimously ruled in favor of middle school students whose attempt to form a GSA had been blocked by the school board, in the case of Carver Middle School Gay–Straight Alliance v. School Board of Lake County, Florida.

History outside the United States

Worldwide, gay–straight alliances are not as common as the organizations are in the United States, but are beginning to spread, particularly in Canada.

Australia

As of July 2020, as reported by the media Star Observer, Australia has one gay–straight alliance set up within the Melbourne Grammar School. However, the United Kingdom, New Zealand, Canada and some parts of the United States have had gay–straight alliances within schools for decades.

In Australia, the group Safe Schools Coalition Victoria piloted a system of reducing homophobia though teacher training and student groups that promote inclusion of LGBT young people, which ran from 2014-2017. Started by The Foundation for Young Australians and Gay and Lesbian Health Victoria, along with La Trobe University, the program was expanded to run Australia wide. The program was supported by Beyondblue, Headspace, the University of Canberra, Macquarie University, University of Western Sydney, Curtin University, various family planning and HIV prevention groups, government bodies and Uniting Church organizations.

Bulgaria

In 2016, Bulgaria became the first country in the Balkans to open a gay–straight alliance in Sofia American College.

Canada

As Canada has two official languages, LGBT student clubs may be referred to as gay–straight alliances (GSA), queer-straight alliances (QSA), alliance allosexuelle-hétérosexuelle (AAH), or alliance gaie-hétéro (AGH).

In May 2010 Egale Canada launched MyGSA.ca, a website focused on GSAs and their role in making Canadian schools safer and more LGBTQ inclusive. Their website includes educational resources for GSAs and information about available bursaries and funding. While MyGSA previously included a directory of registered Canadian GSA, this feature is no longer available on their website. Prior to closing the public directory, more than 283 GSAs had registered with the website.

Currently there are no federal laws in Canada regarding GSAs. Any laws are specific to each province or territory.

British Columbia

The first GSA in Canada was started in 1998 at Pinetree Secondary School in Coquitlam, British Columbia. The start of the Pinetree GSA garnered national media attention, and its members continued to play a role in public affairs by meeting with successive provincial Ministers of Education, testifying before the B.C. Safe Schools Task Force on anti-bullying, and delivering workshops to students and educators about LGBT-sensitive inclusive language and how to start GSAs. In early 2002, the Pinetree GSA held the first Pride Day at a high school in Canada. The Pride Day included an information fair with booths from various local LGBT organizations, PrideTalk workshops delivered in numerous classes, and an assembly with a talk on transgender rights and a performance by G.L.A.S.S., a local LGBT youth choir.

As of 2011, 41% of schools in British Columbia were reported to have a GSA.

Alberta

The first GSA in Alberta was started in 2000 at the Lindsay Thurber Comprehensive High School in Red Deer. While members initially feared backlash, there was little-to-no negative reaction to the club.

In 2011, the Edmonton public school board introduced a policy which mandates that all school principals must establish a GSA if asked for one by students. The same year, the school board assigned a district consultant to provide support for GSAs within the city and host a monthly meeting for GSA members to network.

In 2017, the NDP government of Alberta introduced Bill 24, the Act to Support Gay–Straight Alliances, which mandated that all schools within the province allow student to create a GSA, allow them to explicitly name it a gay–straight alliance or queer-straight alliance, and prohibits school officials from notifying parents if their child joined a GSA. Schools that do not comply with the bill's requirement are subject to lose government funding. Following the release of the bill, there was disapproval from some politicians and parents. In April 2018, the Justice Centre for Constitutional Freedoms (JCCF) filed a Court of Queen's Bench challenge application claiming that prohibiting school officials from notifying parents when their child joins a GSA violates their constitutional rights.

The New Democratic Party of Alberta filibustered for changes to the Bill 8 (The Education Amendment Act) since the United Conservative Party (UCP) defeated all amendments that would protect LGBTQ teachers and staff over their sexual orientation and gender identity. The UCP have removed protections that were in the 2017 Bill 24, Bill 8 allows for students to be outed by school teachers, administration or staff if a student asks for there to be a GSA or QSA. Albertan schools are no longer compelled to act in an urgent manner in the student's request for a GSA or QSA, allowing the school to take as much time as desired without facing penalties that were in Bill 24.

Saskatchewan

In Saskatchewan, Carlton Comprehensive High School houses one of the first GSA movements in the city of Prince Albert. The first GSA in the city of Saskatoon first met on March 18, 2003, at Mount Royal Collegiate. Since then, GSAs have been established at Nutana, Walter Murray, Evan Hardy, Marion Graham, Bedford Road and Aden Bowman Collegiates. The city of North Battleford Saskatchewan, had their first GSA in 2004 at Sakewew High School, a First Nations school.

Saskatchewan's first GSA summit took place on April 15, 2016, in Saskatoon.

Manitoba

In 2013, the Manitoba government introduced Bill 18, The Public Schools Amendment Act (Safe and Inclusive Schools). This act required school board to accommodate all student requests to form GSAs.

Ontario

The first elementary school GSA in Ontario was started in 2008 at the Sunnyside Public School in Kitchener.

In Ontario, Arnprior District High school, a small rural Ottawa Valley town started a GSA created by the students in 2009. This GSA won one of three Jer's Vision "Youth Role Model of The Year" awards in April 2009. The next year a GSA was founded by students in 2010 at Renfrew Collegiate Institute in the town of Renfrew.

In December 2011, the government of the most populous Canadian province, Ontario, announced it would bring a legislation making it mandatory for all publicly funded schools to support the formation of "tolerance clubs" and student associations. Gay–straight clubs were to be specifically mentioned in that act. The main focus of that Bill 14 would be to counterattack bullying of students, particularly those of a racial or sexual minority.

Beyond a school group the Toronto District School Board has been committed to an unwritten alliance with their students. In addition to co-hosting the OUTShine GSA National Summit in 2013, they funded the Triangle Program at OASIS Alternative School, designed for gay, lesbian, bisexual and transgender students who are at risk of dropping out or committing self-harm because of harassment in regular schools.

As of 2011, 37% of schools in Ontario were reported to have a GSA.

Quebec

New Brunswick

In 2008, the non-profit organization Pride in Education was founded to protect the safety and wellbeing of LGBT students in New Brunswick. In 2010, they held the first annual Pride in Education GSA Conference for students and teachers interested in creating GSAs.

The first GSA in New Brunswick was founded in 2013 at Woodstock High School following the suggestion of Svend Robinson.

Prince Edward Island

The University of Prince Edward Island's Social Justice Studies program founded shOUT!, an annual conference aimed as GSAs but open to the public, in 2013.

Nova Scotia

In 1998, The Youth Project, a non-profit focused on LGBT youth in Nova Scotia, received funding from Health Canada to increase education about LGBT in schools. Through this initiative, the organization was able to found the first GSA in Nova Scotia at Millwood High School. The Youth Project currently hosts a list of all GSAs in the province on their website.

Newfoundland and Labrador

The first GSA conference in Newfoundland and Labrador was held at Corner Brook Regional High in 2013.

Yukon

While the Yukon Department of Education does not have specific legislation regarding GSA, it does have a policy which mandates safety and inclusion for LGBT students which has been used in the justification for GSAs. Additionally, the territory mandates that all schools must appoint a staff member as a "safe contact" to provide support for LGBT students.

In 2013, a group of student requested to start a GSA at Vanier Catholic Secondary in Whitehorse. The school initially denied this request as it conflicted with the school's Catholic, anti-gay policies. Students of the school protested the denial by wearing pink shirts and holding a sit-in at the Yukon legislative building and wearing rainbow socks to their graduation ceremony. Following the protests, the Yukon Department of Education overturned the school's policy regarding GSAs as it did not meet the mandates outlines in the department's Sexual Orientation and Gender Identity Policy.

Northwest Territories

Nunavut

The only GSA in Nunavut is at Inuksuk High School in Iqaluit.

Hong Kong

In 2008, students at The University of Hong Kong founded Queer Straight Alliance (QSA), a registered society under Hong Kong laws. For several years it was the only GSA in the city, and it serves students in all campuses through social activities, career support and advocacy. In more recent years, university students in the city have formed other student LGBT groups. However, GSA efforts in secondary schools remain limited, if any.

India

The first GSA in India was started in Tagore International School in New Delhi in 2014 by a group of students and their mentor Shivanee Sen who had formed a pro-LGBT group initiative known as 'Breaking Barriers' which was the first student-led campaign in India to address LGBTQI (lesbian, gay, bisexual, transgender, queer, intersex) issues. This group was first inspired to care and focus on the lives of oppressed students and hijras, a community of transgender women, intersex individuals, and eunuchs in India who are marginalized both socially and economically.

At Presidency University, Kolkata, around 100 students have formed a GSA group called Ardhek Akash, which also produces a magazine of the same name. In recent months the group has formed new chapters at Jadavpur University and St. Xavier's College—also in Calcutta—and is looking to expand further.

Mexico

The first GSA in Mexico was begun by a group of students in 2004 at the American School Foundation, a private American school in Mexico City. The GSA was initially opposed by several school board members and a small group of religious conservative parents. But the students eventually won and formed the student club. The GSA's co-advisor, Ian K. Macgillivray, wrote several articles detailing his students' experiences, as well as the book, Gay–Straight Alliances: A Handbook for Students, Educators, and Parents (2007, Harrington Park Press).

Netherlands

The first GSAs in the Netherlands were started in 2009. At the beginning of 2011, a nationwide campaign was started on television to promote GSAs in Dutch schools, featuring several well-known young actors and singers. A number of GSAs already exist in a wide variety of Dutch schools throughout the country, most of them at the university level, but increasingly popular on secondary school level.

New Zealand

Nelson College, the Nelson College for Girls, Nayland College and other schools have had GSAs set up, often with the support of youth mental health bodies. Kira Byrne, a GSA leader at Nelson College for Girls, says that the legalization of same-sex marriage in New Zealand in 2013 created shifts in attitudes towards LGBT people in New Zealand, but that boys at Nelson College were afraid to go to the GSA there because "other boys would wait outside to beat up anyone that came out."

Portugal

Inspired by the gay–straight alliance model, ILGA Portugal released the project Aliança da Diversidade (ADD), in English "Diversity Alliance", aimed to promote the creation of secondary level student groups (and teachers) from the north of the country.

This aimed to make Portuguese schools safer and more inclusive for everyone regardless of their sexual orientation, gender identity or expression or sex characteristics, the integration of lesbian, gay, bisexual, trans and intersex (LGBTI) students, and the eradication of homo, trans and biphobia, intersexism and gender expression based prejudice and discrimination in the school context, always promoting citizenship, human rights and gender equality.

The project was co-financed by the Programa Operacional de Inclusão Social e Emprego, Portugal 2020 and the European Social Fund.

As a complementary initiative to ADD, the Estudo Nacional sobre o Ambiente Escolar (ENAE), Portuguese for the "National School Environment Study", was launched to collect the experiences of LGBTI or questioning young people. According to Telmo Fernandes, ADD project coordinator, the responses confirmed the persistence of isolation and discrimination, reinforcing the urgency of the change that was intended with the project.

Alianças da Diversidade were created in various schools around the country, such as in Ovar municipality, Ramada parish and in the city of Ermesinde.

The initiative started in mid-2017, formally ending in February 2019, but the maintenance of the groups created so far, as well as the creation of new ones with the same objective could continue independently.

United Kingdom

In the UK, there has always been more of an emphasis on stand alone lesbian and gay youth groups that take place outside of the school setting, often funded by the local health authority or education service. The first GSA in the UK was founded in 2000 by CN Lester at Putney High School GDST, and led in part to the formation of Queer Youth Network. The second GSA in the UK was started in 2010 at Shimna Integrated College in Northern Ireland. Another GSA started in 2012 by Copland Community school in Wembley. The setting up of the club has subsequently resulted in the school being known for "tackling homophobic prejudice". Acland Burghley school in Camden set up a gay–straight alliance in 2012 called Connected.

Central processing unit

From Wikipedia, the free encyclopedia

https://en.wikipedia.org/wiki/Central_processing_unit 

An Intel 80486DX2 CPU, as seen from above

 

Bottom side of an Intel 80486DX2, showing its pins

A central processing unit (CPU), also called a central processor, main processor or just processor, is the electronic circuitry that executes instructions comprising a computer program. The CPU performs basic arithmetic, logic, controlling, and input/output (I/O) operations specified by the instructions in the program. This contrasts with external components such as main memory and I/O circuitry, and specialized processors such as graphics processing units (GPUs).

The form, design, and implementation of CPUs have changed over time, but their fundamental operation remains almost unchanged. Principal components of a CPU include the arithmetic–logic unit (ALU) that performs arithmetic and logic operations, processor registers that supply operands to the ALU and store the results of ALU operations, and a control unit that orchestrates the fetching (from memory), decoding and execution (of instructions) by directing the coordinated operations of the ALU, registers and other components.

Most modern CPUs are implemented on integrated circuit (IC) microprocessors, with one or more CPUs on a single IC chip. Microprocessor chips with multiple CPUs are multi-core processors. The individual physical CPUs, processor cores, can also be multithreaded to create additional virtual or logical CPUs.

An IC that contains a CPU may also contain memory, peripheral interfaces, and other components of a computer; such integrated devices are variously called microcontrollers or systems on a chip (SoC).

Array processors or vector processors have multiple processors that operate in parallel, with no unit considered central. Virtual CPUs are an abstraction of dynamical aggregated computational resources.

History

Main article: History of general-purpose CPUs

 

EDVAC, one of the first stored-program computers

Early computers such as the ENIAC had to be physically rewired to perform different tasks, which caused these machines to be called "fixed-program computers". The "central processing unit" term has been in use since as early as 1955. Since the term "CPU" is generally defined as a device for software (computer program) execution, the earliest devices that could rightly be called CPUs came with the advent of the stored-program computer.

The idea of a stored-program computer had been already present in the design of J. Presper Eckert and John William Mauchly's ENIAC, but was initially omitted so that it could be finished sooner. On June 30, 1945, before ENIAC was made, mathematician John von Neumann distributed the paper entitled First Draft of a Report on the EDVAC. It was the outline of a stored-program computer that would eventually be completed in August 1949. EDVAC was designed to perform a certain number of instructions (or operations) of various types. Significantly, the programs written for EDVAC were to be stored in high-speed computer memory rather than specified by the physical wiring of the computer. This overcame a severe limitation of ENIAC, which was the considerable time and effort required to reconfigure the computer to perform a new task. With von Neumann's design, the program that EDVAC ran could be changed simply by changing the contents of the memory. EDVAC, was not the first stored-program computer, the Manchester Baby which was a small-scale experimental stored-program computer, ran its first program on 21 June 1948 and the Manchester Mark 1 ran its first program during the night of 16–17 June 1949.

Early CPUs were custom designs used as part of a larger and sometimes distinctive computer. However, this method of designing custom CPUs for a particular application has largely given way to the development of multi-purpose processors produced in large quantities. This standardization began in the era of discrete transistor mainframes and minicomputers and has rapidly accelerated with the popularization of the integrated circuit (IC). The IC has allowed increasingly complex CPUs to be designed and manufactured to tolerances on the order of nanometers. Both the miniaturization and standardization of CPUs have increased the presence of digital devices in modern life far beyond the limited application of dedicated computing machines. Modern microprocessors appear in electronic devices ranging from automobiles to cellphones, and sometimes even in toys.

While von Neumann is most often credited with the design of the stored-program computer because of his design of EDVAC, and the design became known as the von Neumann architecture, others before him, such as Konrad Zuse, had suggested and implemented similar ideas. The so-called Harvard architecture of the Harvard Mark I, which was completed before EDVAC, also used a stored-program design using punched paper tape rather than electronic memory. The key difference between the von Neumann and Harvard architectures is that the latter separates the storage and treatment of CPU instructions and data, while the former uses the same memory space for both. Most modern CPUs are primarily von Neumann in design, but CPUs with the Harvard architecture are seen as well, especially in embedded applications; for instance, the Atmel AVR microcontrollers are Harvard architecture processors.

Relays and vacuum tubes (thermionic tubes) were commonly used as switching elements; a useful computer requires thousands or tens of thousands of switching devices. The overall speed of a system is dependent on the speed of the switches. Vacuum-tube computers such as EDVAC tended to average eight hours between failures, whereas relay computers like the (slower, but earlier) Harvard Mark I failed very rarely. In the end, tube-based CPUs became dominant because the significant speed advantages afforded generally outweighed the reliability problems. Most of these early synchronous CPUs ran at low clock rates compared to modern microelectronic designs. Clock signal frequencies ranging from 100 kHz to 4 MHz were very common at this time, limited largely by the speed of the switching devices they were built with.

Transistor CPUs

IBM PowerPC 604e processor

 

Main article: Transistor computer

The design complexity of CPUs increased as various technologies facilitated building smaller and more reliable electronic devices. The first such improvement came with the advent of the transistor. Transistorized CPUs during the 1950s and 1960s no longer had to be built out of bulky, unreliable and fragile switching elements like vacuum tubes and relays. With this improvement, more complex and reliable CPUs were built onto one or several printed circuit boards containing discrete (individual) components.

In 1964, IBM introduced its IBM System/360 computer architecture that was used in a series of computers capable of running the same programs with different speed and performance. This was significant at a time when most electronic computers were incompatible with one another, even those made by the same manufacturer. To facilitate this improvement, IBM used the concept of a microprogram (often called "microcode"), which still sees widespread usage in modern CPUs. The System/360 architecture was so popular that it dominated the mainframe computer market for decades and left a legacy that is still continued by similar modern computers like the IBM zSeries. In 1965, Digital Equipment Corporation (DEC) introduced another influential computer aimed at the scientific and research markets, the PDP-8.

Fujitsu board with SPARC64 VIIIfx processors

Transistor-based computers had several distinct advantages over their predecessors. Aside from facilitating increased reliability and lower power consumption, transistors also allowed CPUs to operate at much higher speeds because of the short switching time of a transistor in comparison to a tube or relay. The increased reliability and dramatically increased speed of the switching elements (which were almost exclusively transistors by this time); CPU clock rates in the tens of megahertz were easily obtained during this period. Additionally, while discrete transistor and IC CPUs were in heavy usage, new high-performance designs like single instruction, multiple data (SIMD) vector processors began to appear. These early experimental designs later gave rise to the era of specialized supercomputers like those made by Cray Inc and Fujitsu Ltd.

Small-scale integration CPUs

CPU, core memory and external bus interface of a DEC PDP-8/I, made of medium-scale integrated circuits

During this period, a method of manufacturing many interconnected transistors in a compact space was developed. The integrated circuit (IC) allowed a large number of transistors to be manufactured on a single semiconductor-based die, or "chip". At first, only very basic non-specialized digital circuits such as NOR gates were miniaturized into ICs. CPUs based on these "building block" ICs are generally referred to as "small-scale integration" (SSI) devices. SSI ICs, such as the ones used in the Apollo Guidance Computer, usually contained up to a few dozen transistors. To build an entire CPU out of SSI ICs required thousands of individual chips, but still consumed much less space and power than earlier discrete transistor designs.

IBM's System/370, follow-on to the System/360, used SSI ICs rather than Solid Logic Technology discrete-transistor modules. DEC's PDP-8/I and KI10 PDP-10 also switched from the individual transistors used by the PDP-8 and PDP-10 to SSI ICs, and their extremely popular PDP-11 line was originally built with SSI ICs but was eventually implemented with LSI components once these became practical.

Large-scale integration CPUs

Lee Boysel published influential articles, including a 1967 "manifesto", which described how to build the equivalent of a 32-bit mainframe computer from a relatively small number of large-scale integration circuits (LSI). The only way to build LSI chips, which are chips with a hundred or more gates, was to build them using a metal–oxide–semiconductor (MOS) semiconductor manufacturing process (either PMOS logic, NMOS logic, or CMOS logic). However, some companies continued to build processors out of bipolar transistor–transistor logic (TTL) chips because bipolar junction transistors were faster than MOS chips up until the 1970s (a few companies such as Datapoint continued to build processors out of TTL chips until the early 1980s). In the 1960s, MOS ICs were slower and initially considered useful only in applications that required low power. Following the development of silicon-gate MOS technology by Federico Faggin at Fairchild Semiconductor in 1968, MOS ICs largely replaced bipolar TTL as the standard chip technology in the early 1970s.

As the microelectronic technology advanced, an increasing number of transistors were placed on ICs, decreasing the number of individual ICs needed for a complete CPU. MSI and LSI ICs increased transistor counts to hundreds, and then thousands. By 1968, the number of ICs required to build a complete CPU had been reduced to 24 ICs of eight different types, with each IC containing roughly 1000 MOSFETs. In stark contrast with its SSI and MSI predecessors, the first LSI implementation of the PDP-11 contained a CPU composed of only four LSI integrated circuits.

Microprocessors

Main article: Microprocessor

 

Die of an Intel 80486DX2 microprocessor (actual size: 12 × 6.75 mm) in its packaging

 

Intel Core i5 CPU on a Vaio E series laptop motherboard (on the right, beneath the heat pipe)

 

Inside of a laptop, with the CPU removed from socket

Since microprocessors were first introduced they have almost completely overtaken all other central processing unit implementation methods. The first commercially available microprocessor, made in 1971, was the Intel 4004, and the first widely used microprocessor, made in 1974, was the Intel 8080. Mainframe and minicomputer manufacturers of the time launched proprietary IC development programs to upgrade their older computer architectures, and eventually produced instruction set compatible microprocessors that were backward-compatible with their older hardware and software. Combined with the advent and eventual success of the ubiquitous personal computer, the term CPU is now applied almost exclusively to microprocessors. Several CPUs (denoted cores) can be combined in a single processing chip.

Previous generations of CPUs were implemented as discrete components and numerous small integrated circuits (ICs) on one or more circuit boards. Microprocessors, on the other hand, are CPUs manufactured on a very small number of ICs; usually just one. The overall smaller CPU size, as a result of being implemented on a single die, means faster switching time because of physical factors like decreased gate parasitic capacitance. This has allowed synchronous microprocessors to have clock rates ranging from tens of megahertz to several gigahertz. Additionally, the ability to construct exceedingly small transistors on an IC has increased the complexity and number of transistors in a single CPU many fold. This widely observed trend is described by Moore's law, which had proven to be a fairly accurate predictor of the growth of CPU (and other IC) complexity until 2016.

While the complexity, size, construction and general form of CPUs have changed enormously since 1950, the basic design and function has not changed much at all. Almost all common CPUs today can be very accurately described as von Neumann stored-program machines. As Moore's law no longer holds, concerns have arisen about the limits of integrated circuit transistor technology. Extreme miniaturization of electronic gates is causing the effects of phenomena like electromigration and subthreshold leakage to become much more significant. These newer concerns are among the many factors causing researchers to investigate new methods of computing such as the quantum computer, as well as to expand the usage of parallelism and other methods that extend the usefulness of the classical von Neumann model.

Operation

The fundamental operation of most CPUs, regardless of the physical form they take, is to execute a sequence of stored instructions that is called a program. The instructions to be executed are kept in some kind of computer memory. Nearly all CPUs follow the fetch, decode and execute steps in their operation, which are collectively known as the instruction cycle.

After the execution of an instruction, the entire process repeats, with the next instruction cycle normally fetching the next-in-sequence instruction because of the incremented value in the program counter. If a jump instruction was executed, the program counter will be modified to contain the address of the instruction that was jumped to and program execution continues normally. In more complex CPUs, multiple instructions can be fetched, decoded and executed simultaneously. This section describes what is generally referred to as the "classic RISC pipeline", which is quite common among the simple CPUs used in many electronic devices (often called microcontrollers). It largely ignores the important role of CPU cache, and therefore the access stage of the pipeline.

Some instructions manipulate the program counter rather than producing result data directly; such instructions are generally called "jumps" and facilitate program behavior like loops, conditional program execution (through the use of a conditional jump), and existence of functions. In some processors, some other instructions change the state of bits in a "flags" register. These flags can be used to influence how a program behaves, since they often indicate the outcome of various operations. For example, in such processors a "compare" instruction evaluates two values and sets or clears bits in the flags register to indicate which one is greater or whether they are equal; one of these flags could then be used by a later jump instruction to determine program flow.

Fetch

Fetch involves retrieving an instruction (which is represented by a number or sequence of numbers) from program memory. The instruction's location (address) in program memory is determined by the program counter (PC; called the "instruction pointer" in Intel x86 microprocessors), which stores a number that identifies the address of the next instruction to be fetched. After an instruction is fetched, the PC is incremented by the length of the instruction so that it will contain the address of the next instruction in the sequence. Often, the instruction to be fetched must be retrieved from relatively slow memory, causing the CPU to stall while waiting for the instruction to be returned. This issue is largely addressed in modern processors by caches and pipeline architectures (see below).

Decode

Further information: Instruction set architecture § Instruction encoding

The instruction that the CPU fetches from memory determines what the CPU will do. In the decode step, performed by binary decoder circuitry known as the instruction decoder, the instruction is converted into signals that control other parts of the CPU.

The way in which the instruction is interpreted is defined by the CPU's instruction set architecture (ISA). Often, one group of bits (that is, a "field") within the instruction, called the opcode, indicates which operation is to be performed, while the remaining fields usually provide supplemental information required for the operation, such as the operands. Those operands may be specified as a constant value (called an immediate value), or as the location of a value that may be a processor register or a memory address, as determined by some addressing mode.

In some CPU designs the instruction decoder is implemented as a hardwired, unchangeable binary decoder circuit. In others, a microprogram is used to translate instructions into sets of CPU configuration signals that are applied sequentially over multiple clock pulses. In some cases the memory that stores the microprogram is rewritable, making it possible to change the way in which the CPU decodes instructions.

Execute

After the fetch and decode steps, the execute step is performed. Depending on the CPU architecture, this may consist of a single action or a sequence of actions. During each action, control signals electrically enable or disable various parts of the CPU so they can perform all or part of the desired operation. The action is then completed, typically in response to a clock pulse. Very often the results are written to an internal CPU register for quick access by subsequent instructions. In other cases results may be written to slower, but less expensive and higher capacity main memory.

For example, if an addition instruction is to be executed, registers containing operands (numbers to be summed) are activated, as are the parts of the arithmetic logic unit (ALU) that perform addition. When the clock pulse occurs, the operands flow from the source registers into the ALU, and the sum appears at its output. On subsequent clock pulses, other components are enabled (and disabled) to move the output (the sum of the operation) to storage (e.g., a register or memory). If the resulting sum is too large (i.e., it is larger than the ALU's output word size), an arithmetic overflow flag will be set, influencing the next operation.

Structure and implementation

See also: Processor design

 

Block diagram of a basic uniprocessor-CPU computer. Black lines indicate data flow, whereas red lines indicate control flow; arrows indicate flow directions.

Hardwired into a CPU's circuitry is a set of basic operations it can perform, called an instruction set. Such operations may involve, for example, adding or subtracting two numbers, comparing two numbers, or jumping to a different part of a program. Each instruction is represented by a unique combination of bits, known as the machine language opcode. While processing an instruction, the CPU decodes the opcode (via a binary decoder) into control signals, which orchestrate the behavior of the CPU. A complete machine language instruction consists of an opcode and, in many cases, additional bits that specify arguments for the operation (for example, the numbers to be summed in the case of an addition operation). Going up the complexity scale, a machine language program is a collection of machine language instructions that the CPU executes.

The actual mathematical operation for each instruction is performed by a combinational logic circuit within the CPU's processor known as the arithmetic–logic unit or ALU. In general, a CPU executes an instruction by fetching it from memory, using its ALU to perform an operation, and then storing the result to memory. Beside the instructions for integer mathematics and logic operations, various other machine instructions exist, such as those for loading data from memory and storing it back, branching operations, and mathematical operations on floating-point numbers performed by the CPU's floating-point unit (FPU).

Control unit

Main article: Control unit

The control unit (CU) is a component of the CPU that directs the operation of the processor. It tells the computer's memory, arithmetic and logic unit and input and output devices how to respond to the instructions that have been sent to the processor.

It directs the operation of the other units by providing timing and control signals. Most computer resources are managed by the CU. It directs the flow of data between the CPU and the other devices. John von Neumann included the control unit as part of the von Neumann architecture. In modern computer designs, the control unit is typically an internal part of the CPU with its overall role and operation unchanged since its introduction.

Arithmetic logic unit

Main article: Arithmetic logic unit

 

Symbolic representation of an ALU and its input and output signals

The arithmetic logic unit (ALU) is a digital circuit within the processor that performs integer arithmetic and bitwise logic operations. The inputs to the ALU are the data words to be operated on (called operands), status information from previous operations, and a code from the control unit indicating which operation to perform. Depending on the instruction being executed, the operands may come from internal CPU registers, external memory, or constants generated by the ALU itself.

When all input signals have settled and propagated through the ALU circuitry, the result of the performed operation appears at the ALU's outputs. The result consists of both a data word, which may be stored in a register or memory, and status information that is typically stored in a special, internal CPU register reserved for this purpose.

Address generation unit

Main article: Address generation unit

Address generation unit (AGU), sometimes also called address computation unit (ACU), is an execution unit inside the CPU that calculates addresses used by the CPU to access main memory. By having address calculations handled by separate circuitry that operates in parallel with the rest of the CPU, the number of CPU cycles required for executing various machine instructions can be reduced, bringing performance improvements.

While performing various operations, CPUs need to calculate memory addresses required for fetching data from the memory; for example, in-memory positions of array elements must be calculated before the CPU can fetch the data from actual memory locations. Those address-generation calculations involve different integer arithmetic operations, such as addition, subtraction, modulo operations, or bit shifts. Often, calculating a memory address involves more than one general-purpose machine instruction, which do not necessarily decode and execute quickly. By incorporating an AGU into a CPU design, together with introducing specialized instructions that use the AGU, various address-generation calculations can be offloaded from the rest of the CPU, and can often be executed quickly in a single CPU cycle.

Capabilities of an AGU depend on a particular CPU and its architecture. Thus, some AGUs implement and expose more address-calculation operations, while some also include more advanced specialized instructions that can operate on multiple operands at a time. Some CPU architectures include multiple AGUs so more than one address-calculation operation can be executed simultaneously, which brings further performance improvements due to the superscalar nature of advanced CPU designs. For example, Intel incorporates multiple AGUs into its Sandy Bridge and Haswell microarchitectures, which increase bandwidth of the CPU memory subsystem by allowing multiple memory-access instructions to be executed in parallel.

Memory management unit (MMU)

Main article: Memory management unit

Many microprocessors (in smartphones and desktop, laptop, server computers) have a memory management unit, translating logical addresses into physical RAM addresses, providing memory protection and paging abilities, useful for virtual memory. Simpler processors, especially microcontrollers, usually don't include an MMU.

Cache

A CPU cache is a hardware cache used by the central processing unit (CPU) of a computer to reduce the average cost (time or energy) to access data from the main memory. A cache is a smaller, faster memory, closer to a processor core, which stores copies of the data from frequently used main memory locations. Most CPUs have different independent caches, including instruction and data caches, where the data cache is usually organized as a hierarchy of more cache levels (L1, L2, L3, L4, etc.).

All modern (fast) CPUs (with few specialized exceptions) have multiple levels of CPU caches. The first CPUs that used a cache had only one level of cache; unlike later level 1 caches, it was not split into L1d (for data) and L1i (for instructions). Almost all current CPUs with caches have a split L1 cache. They also have L2 caches and, for larger processors, L3 caches as well. The L2 cache is usually not split and acts as a common repository for the already split L1 cache. Every core of a multi-core processor has a dedicated L2 cache and is usually not shared between the cores. The L3 cache, and higher-level caches, are shared between the cores and are not split. An L4 cache is currently uncommon, and is generally on dynamic random-access memory (DRAM), rather than on static random-access memory (SRAM), on a separate die or chip. That was also the case historically with L1, while bigger chips have allowed integration of it and generally all cache levels, with the possible exception of the last level. Each extra level of cache tends to be bigger and be optimized differently.

Other types of caches exist (that are not counted towards the "cache size" of the most important caches mentioned above), such as the translation lookaside buffer (TLB) that is part of the memory management unit (MMU) that most CPUs have.

Caches are generally sized in powers of two: 2, 8, 16 etc. KiB or MiB (for larger non-L1) sizes, although the IBM z13 has a 96 KiB L1 instruction cache.

Clock rate

Main article: Clock rate

Most CPUs are synchronous circuits, which means they employ a clock signal to pace their sequential operations. The clock signal is produced by an external oscillator circuit that generates a consistent number of pulses each second in the form of a periodic square wave. The frequency of the clock pulses determines the rate at which a CPU executes instructions and, consequently, the faster the clock, the more instructions the CPU will execute each second.

To ensure proper operation of the CPU, the clock period is longer than the maximum time needed for all signals to propagate (move) through the CPU. In setting the clock period to a value well above the worst-case propagation delay, it is possible to design the entire CPU and the way it moves data around the "edges" of the rising and falling clock signal. This has the advantage of simplifying the CPU significantly, both from a design perspective and a component-count perspective. However, it also carries the disadvantage that the entire CPU must wait on its slowest elements, even though some portions of it are much faster. This limitation has largely been compensated for by various methods of increasing CPU parallelism (see below).

However, architectural improvements alone do not solve all of the drawbacks of globally synchronous CPUs. For example, a clock signal is subject to the delays of any other electrical signal. Higher clock rates in increasingly complex CPUs make it more difficult to keep the clock signal in phase (synchronized) throughout the entire unit. This has led many modern CPUs to require multiple identical clock signals to be provided to avoid delaying a single signal significantly enough to cause the CPU to malfunction. Another major issue, as clock rates increase dramatically, is the amount of heat that is dissipated by the CPU. The constantly changing clock causes many components to switch regardless of whether they are being used at that time. In general, a component that is switching uses more energy than an element in a static state. Therefore, as clock rate increases, so does energy consumption, causing the CPU to require more heat dissipation in the form of CPU cooling solutions.

One method of dealing with the switching of unneeded components is called clock gating, which involves turning off the clock signal to unneeded components (effectively disabling them). However, this is often regarded as difficult to implement and therefore does not see common usage outside of very low-power designs. One notable recent CPU design that uses extensive clock gating is the IBM PowerPC-based Xenon used in the Xbox 360; that way, power requirements of the Xbox 360 are greatly reduced.

Clockless CPUs

Another method of addressing some of the problems with a global clock signal is the removal of the clock signal altogether. While removing the global clock signal makes the design process considerably more complex in many ways, asynchronous (or clockless) designs carry marked advantages in power consumption and heat dissipation in comparison with similar synchronous designs. While somewhat uncommon, entire asynchronous CPUs have been built without using a global clock signal. Two notable examples of this are the ARM compliant AMULET and the MIPS R3000 compatible MiniMIPS.

Rather than totally removing the clock signal, some CPU designs allow certain portions of the device to be asynchronous, such as using asynchronous ALUs in conjunction with superscalar pipelining to achieve some arithmetic performance gains. While it is not altogether clear whether totally asynchronous designs can perform at a comparable or better level than their synchronous counterparts, it is evident that they do at least excel in simpler math operations. This, combined with their excellent power consumption and heat dissipation properties, makes them very suitable for embedded computers.

Voltage regulator module

Main article: Voltage regulator module

Many modern CPUs have a die-integrated power managing module which regulates on-demand voltage supply to the CPU circuitry allowing it to keep balance between performance and power consumption.

Integer range

Every CPU represents numerical values in a specific way. For example, some early digital computers represented numbers as familiar decimal (base 10) numeral system values, and others have employed more unusual representations such as ternary (base three). Nearly all modern CPUs represent numbers in binary form, with each digit being represented by some two-valued physical quantity such as a "high" or "low" voltage.

A six-bit word containing the binary encoded representation of decimal value 40. Most modern CPUs employ word sizes that are a power of two, for example 8, 16, 32 or 64 bits.

Related to numeric representation is the size and precision of integer numbers that a CPU can represent. In the case of a binary CPU, this is measured by the number of bits (significant digits of a binary encoded integer) that the CPU can process in one operation, which is commonly called word size, bit width, data path width, integer precision, or integer size. A CPU's integer size determines the range of integer values it can directly operate on. For example, an 8-bit CPU can directly manipulate integers represented by eight bits, which have a range of 256 (2⁸) discrete integer values.

Integer range can also affect the number of memory locations the CPU can directly address (an address is an integer value representing a specific memory location). For example, if a binary CPU uses 32 bits to represent a memory address then it can directly address 2³² memory locations. To circumvent this limitation and for various other reasons, some CPUs use mechanisms (such as bank switching) that allow additional memory to be addressed.

CPUs with larger word sizes require more circuitry and consequently are physically larger, cost more and consume more power (and therefore generate more heat). As a result, smaller 4- or 8-bit microcontrollers are commonly used in modern applications even though CPUs with much larger word sizes (such as 16, 32, 64, even 128-bit) are available. When higher performance is required, however, the benefits of a larger word size (larger data ranges and address spaces) may outweigh the disadvantages. A CPU can have internal data paths shorter than the word size to reduce size and cost. For example, even though the IBM System/360 instruction set was a 32-bit instruction set, the System/360 Model 30 and Model 40 had 8-bit data paths in the arithmetic logical unit, so that a 32-bit add required four cycles, one for each 8 bits of the operands, and, even though the Motorola 68000 series instruction set was a 32-bit instruction set, the Motorola 68000 and Motorola 68010 had 16-bit data paths in the arithmetic logical unit, so that a 32-bit add required two cycles.

To gain some of the advantages afforded by both lower and higher bit lengths, many instruction sets have different bit widths for integer and floating-point data, allowing CPUs implementing that instruction set to have different bit widths for different portions of the device. For example, the IBM System/360 instruction set was primarily 32 bit, but supported 64-bit floating-point values to facilitate greater accuracy and range in floating-point numbers. The System/360 Model 65 had an 8-bit adder for decimal and fixed-point binary arithmetic and a 60-bit adder for floating-point arithmetic. Many later CPU designs use similar mixed bit width, especially when the processor is meant for general-purpose usage where a reasonable balance of integer and floating-point capability is required.

Parallelism

Main article: Parallel computing

 

Model of a subscalar CPU, in which it takes fifteen clock cycles to complete three instructions

The description of the basic operation of a CPU offered in the previous section describes the simplest form that a CPU can take. This type of CPU, usually referred to as subscalar, operates on and executes one instruction on one or two pieces of data at a time, that is less than one instruction per clock cycle (IPC < 1).

This process gives rise to an inherent inefficiency in subscalar CPUs. Since only one instruction is executed at a time, the entire CPU must wait for that instruction to complete before proceeding to the next instruction. As a result, the subscalar CPU gets "hung up" on instructions which take more than one clock cycle to complete execution. Even adding a second execution unit (see below) does not improve performance much; rather than one pathway being hung up, now two pathways are hung up and the number of unused transistors is increased. This design, wherein the CPU's execution resources can operate on only one instruction at a time, can only possibly reach scalar performance (one instruction per clock cycle, IPC = 1). However, the performance is nearly always subscalar (less than one instruction per clock cycle, IPC < 1).

Attempts to achieve scalar and better performance have resulted in a variety of design methodologies that cause the CPU to behave less linearly and more in parallel. When referring to parallelism in CPUs, two terms are generally used to classify these design techniques:

• instruction-level parallelism (ILP), which seeks to increase the rate at which instructions are executed within a CPU (that is, to increase the use of on-die execution resources);
• task-level parallelism (TLP), which purposes to increase the number of threads or processes that a CPU can execute simultaneously.

Each methodology differs both in the ways in which they are implemented, as well as the relative effectiveness they afford in increasing the CPU's performance for an application.

Instruction-level parallelism

Main article: Instruction-level parallelism

 

Basic five-stage pipeline. In the best case scenario, this pipeline can sustain a completion rate of one instruction per clock cycle.

One of the simplest methods for increased parallelism is to begin the first steps of instruction fetching and decoding before the prior instruction finishes executing. This is a technique known as instruction pipelining, and is used in almost all modern general-purpose CPUs. Pipelining allows multiple instruction to be executed at a time by breaking the execution pathway into discrete stages. This separation can be compared to an assembly line, in which an instruction is made more complete at each stage until it exits the execution pipeline and is retired.

Pipelining does, however, introduce the possibility for a situation where the result of the previous operation is needed to complete the next operation; a condition often termed data dependency conflict. Therefore pipelined processors must check for these sorts of conditions and delay a portion of the pipeline if necessary. A pipelined processor can become very nearly scalar, inhibited only by pipeline stalls (an instruction spending more than one clock cycle in a stage).

A simple superscalar pipeline. By fetching and dispatching two instructions at a time, a maximum of two instructions per clock cycle can be completed.

Improvements in instruction pipelining led to further decreases in the idle time of CPU components. Designs that are said to be superscalar include a long instruction pipeline and multiple identical execution units, such as load–store units, arithmetic–logic units, floating-point units and address generation units. In a superscalar pipeline, instructions are read and passed to a dispatcher, which decides whether or not the instructions can be executed in parallel (simultaneously). If so, they are dispatched to execution units, resulting in their simultaneous execution. In general, the number of instructions that a superscalar CPU will complete in a cycle is dependent on the number of instructions it is able to dispatch simultaneously to execution units.

Most of the difficulty in the design of a superscalar CPU architecture lies in creating an effective dispatcher. The dispatcher needs to be able to quickly determine whether instructions can be executed in parallel, as well as dispatch them in such a way as to keep as many execution units busy as possible. This requires that the instruction pipeline is filled as often as possible and requires significant amounts of CPU cache. It also makes hazard-avoiding techniques like branch prediction, speculative execution, register renaming, out-of-order execution and transactional memory crucial to maintaining high levels of performance. By attempting to predict which branch (or path) a conditional instruction will take, the CPU can minimize the number of times that the entire pipeline must wait until a conditional instruction is completed. Speculative execution often provides modest performance increases by executing portions of code that may not be needed after a conditional operation completes. Out-of-order execution somewhat rearranges the order in which instructions are executed to reduce delays due to data dependencies. Also in case of single instruction stream, multiple data stream—a case when a lot of data from the same type has to be processed—, modern processors can disable parts of the pipeline so that when a single instruction is executed many times, the CPU skips the fetch and decode phases and thus greatly increases performance on certain occasions, especially in highly monotonous program engines such as video creation software and photo processing.

When just a fraction of the CPU is superscalar, the part that is not suffers a performance penalty due to scheduling stalls. The Intel P5 Pentium had two superscalar ALUs which could accept one instruction per clock cycle each, but its FPU could not. Thus the P5 was integer superscalar but not floating point superscalar. Intel's successor to the P5 architecture, P6, added superscalar abilities to its floating-point features.

Simple pipelining and superscalar design increase a CPU's ILP by allowing it to execute instructions at rates surpassing one instruction per clock cycle. Most modern CPU designs are at least somewhat superscalar, and nearly all general purpose CPUs designed in the last decade are superscalar. In later years some of the emphasis in designing high-ILP computers has been moved out of the CPU's hardware and into its software interface, or instruction set architecture (ISA). The strategy of the very long instruction word (VLIW) causes some ILP to become implied directly by the software, reducing the CPU’s work in boosting ILP and thereby reducing design complexity.

Task-level parallelism

Main articles: Multithreading and Multi-core processor

Another strategy of achieving performance is to execute multiple threads or processes in parallel. This area of research is known as parallel computing. In Flynn's taxonomy, this strategy is known as multiple instruction stream, multiple data stream (MIMD).

One technology used for this purpose was multiprocessing (MP). The initial flavor of this technology is known as symmetric multiprocessing (SMP), where a small number of CPUs share a coherent view of their memory system. In this scheme, each CPU has additional hardware to maintain a constantly up-to-date view of memory. By avoiding stale views of memory, the CPUs can cooperate on the same program and programs can migrate from one CPU to another. To increase the number of cooperating CPUs beyond a handful, schemes such as non-uniform memory access (NUMA) and directory-based coherence protocols were introduced in the 1990s. SMP systems are limited to a small number of CPUs while NUMA systems have been built with thousands of processors. Initially, multiprocessing was built using multiple discrete CPUs and boards to implement the interconnect between the processors. When the processors and their interconnect are all implemented on a single chip, the technology is known as chip-level multiprocessing (CMP) and the single chip as a multi-core processor.

It was later recognized that finer-grain parallelism existed with a single program. A single program might have several threads (or functions) that could be executed separately or in parallel. Some of the earliest examples of this technology implemented input/output processing such as direct memory access as a separate thread from the computation thread. A more general approach to this technology was introduced in the 1970s when systems were designed to run multiple computation threads in parallel. This technology is known as multi-threading (MT). This approach is considered more cost-effective than multiprocessing, as only a small number of components within a CPU is replicated to support MT as opposed to the entire CPU in the case of MP. In MT, the execution units and the memory system including the caches are shared among multiple threads. The downside of MT is that the hardware support for multithreading is more visible to software than that of MP and thus supervisor software like operating systems have to undergo larger changes to support MT. One type of MT that was implemented is known as temporal multithreading, where one thread is executed until it is stalled waiting for data to return from external memory. In this scheme, the CPU would then quickly context switch to another thread which is ready to run, the switch often done in one CPU clock cycle, such as the UltraSPARC T1. Another type of MT is simultaneous multithreading, where instructions from multiple threads are executed in parallel within one CPU clock cycle.

For several decades from the 1970s to early 2000s, the focus in designing high performance general purpose CPUs was largely on achieving high ILP through technologies such as pipelining, caches, superscalar execution, out-of-order execution, etc. This trend culminated in large, power-hungry CPUs such as the Intel Pentium 4. By the early 2000s, CPU designers were thwarted from achieving higher performance from ILP techniques due to the growing disparity between CPU operating frequencies and main memory operating frequencies as well as escalating CPU power dissipation owing to more esoteric ILP techniques.

CPU designers then borrowed ideas from commercial computing markets such as transaction processing, where the aggregate performance of multiple programs, also known as throughput computing, was more important than the performance of a single thread or process.

This reversal of emphasis is evidenced by the proliferation of dual and more core processor designs and notably, Intel's newer designs resembling its less superscalar P6 architecture. Late designs in several processor families exhibit CMP, including the x86-64 Opteron and Athlon 64 X2, the SPARC UltraSPARC T1, IBM POWER4 and POWER5, as well as several video game console CPUs like the Xbox 360's triple-core PowerPC design, and the PlayStation 3's 7-core Cell microprocessor.

Data parallelism

Main articles: Vector processor and SIMD

A less common but increasingly important paradigm of processors (and indeed, computing in general) deals with data parallelism. The processors discussed earlier are all referred to as some type of scalar device. As the name implies, vector processors deal with multiple pieces of data in the context of one instruction. This contrasts with scalar processors, which deal with one piece of data for every instruction. Using Flynn's taxonomy, these two schemes of dealing with data are generally referred to as single instruction stream, multiple data stream (SIMD) and single instruction stream, single data stream (SISD), respectively. The great utility in creating processors that deal with vectors of data lies in optimizing tasks that tend to require the same operation (for example, a sum or a dot product) to be performed on a large set of data. Some classic examples of these types of tasks include multimedia applications (images, video and sound), as well as many types of scientific and engineering tasks. Whereas a scalar processor must complete the entire process of fetching, decoding and executing each instruction and value in a set of data, a vector processor can perform a single operation on a comparatively large set of data with one instruction. This is only possible when the application tends to require many steps which apply one operation to a large set of data.

Most early vector processors, such as the Cray-1, were associated almost exclusively with scientific research and cryptography applications. However, as multimedia has largely shifted to digital media, the need for some form of SIMD in general-purpose processors has become significant. Shortly after inclusion of floating-point units started to become commonplace in general-purpose processors, specifications for and implementations of SIMD execution units also began to appear for general-purpose processors. Some of these early SIMD specifications – like HP's Multimedia Acceleration eXtensions (MAX) and Intel's MMX – were integer-only. This proved to be a significant impediment for some software developers, since many of the applications that benefit from SIMD primarily deal with floating-point numbers. Progressively, developers refined and remade these early designs into some of the common modern SIMD specifications, which are usually associated with one instruction set architecture (ISA). Some notable modern examples include Intel's Streaming SIMD Extensions (SSE) and the PowerPC-related AltiVec (also known as VMX).

Hardware performance counter

Main article: Hardware performance counter

Many modern architectures (including embedded ones) often include hardware performance counters (HPC), which enables low-level (instruction-level) collection, benchmarking, debugging or analysis of running software metrics. HPC may also be used to discover and analyze unusual or suspicious activity of the software, such as return-oriented programming (ROP) or sigreturn-oriented programming (SROP) exploits etc. This is usually done by software-security teams to assess and find malicious binary programs.

Many major vendors (such as IBM, Intel, AMD, and ARM etc.) provide software interfaces (usually written in C/C++) that can be used to collected data from CPUs registers in order to get metrics. Operating system vendors also provide software like perf (Linux) to record, benchmark, or trace CPU events running kernels and applications.

Virtual CPUs

Cloud computing can involve subdividing CPU operation into virtual central processing units (vCPUs).

A host is the virtual equivalent of a physical machine, on which a virtual system is operating. When there are several physical machines operating in tandem and managed as a whole, the grouped computing and memory resources form a cluster. In some systems, it is possible to dynamically add and remove from a cluster. Resources available at a host and cluster level can be partitioned out into resources pools with fine granularity.

Performance

Further information: Computer performance and Benchmark (computing)

The performance or speed of a processor depends on, among many other factors, the clock rate (generally given in multiples of hertz) and the instructions per clock (IPC), which together are the factors for the instructions per second (IPS) that the CPU can perform. Many reported IPS values have represented "peak" execution rates on artificial instruction sequences with few branches, whereas realistic workloads consist of a mix of instructions and applications, some of which take longer to execute than others. The performance of the memory hierarchy also greatly affects processor performance, an issue barely considered in MIPS calculations. Because of these problems, various standardized tests, often called "benchmarks" for this purpose‍—‌such as SPECint‍—‌have been developed to attempt to measure the real effective performance in commonly used applications.

Processing performance of computers is increased by using multi-core processors, which essentially is plugging two or more individual processors (called cores in this sense) into one integrated circuit. Ideally, a dual core processor would be nearly twice as powerful as a single core processor. In practice, the performance gain is far smaller, only about 50%, due to imperfect software algorithms and implementation. Increasing the number of cores in a processor (i.e. dual-core, quad-core, etc.) increases the workload that can be handled. This means that the processor can now handle numerous asynchronous events, interrupts, etc. which can take a toll on the CPU when overwhelmed. These cores can be thought of as different floors in a processing plant, with each floor handling a different task. Sometimes, these cores will handle the same tasks as cores adjacent to them if a single core is not enough to handle the information.

Due to specific capabilities of modern CPUs, such as simultaneous multithreading and uncore, which involve sharing of actual CPU resources while aiming at increased utilization, monitoring performance levels and hardware use gradually became a more complex task. As a response, some CPUs implement additional hardware logic that monitors actual use of various parts of a CPU and provides various counters accessible to software; an example is Intel's Performance Counter Monitor technology.