Science and technology studies

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https://en.wikipedia.org/wiki/Science_and_technology_studies 

A communications artifact (Rugby Aerial Tuning Inductor) at the Science Museum, London, UK

Science and technology studies (STS) or science, technology, and society is an interdisciplinary field that examines the creation, development, and consequences of science and technology in their historical, cultural, and social contexts.

History

Like most interdisciplinary fields of study, STS emerged from the confluence of disciplines and disciplinary subfields, all of which had developed an interest—typically, during the 1960s or 1970s—in viewing science and technology as socially embedded enterprises. The key disciplinary components of STS took shape independently, beginning in the 1960s, and developed in isolation from each other well into the 1980s, although Ludwik Fleck's (1935) monograph Genesis and Development of a Scientific Fact anticipated many of STS's key themes. In the 1970s Elting E. Morison founded the STS program at the Massachusetts Institute of Technology (MIT), which served as a model. By 2011, 111 STS research centers and academic programs were counted worldwide.

Important key points

• History of technology, that examines technology in its social and historical context. Starting in the 1960s, some historians questioned technological determinism, a doctrine that can induce public passivity to technologic and scientific "natural" development. At the same time, some historians began to develop similarly contextual approaches to the history of medicine. Notable historians of medicine who approach the field from a science and technology studies perspective include Robert N. Proctor.
• History and philosophy of science (1960s). After the publication of Thomas Kuhn's well-known The Structure of Scientific Revolutions (1962), which attributed changes in scientific theories to changes in underlying intellectual paradigms, programs were founded at the University of California, Berkeley and elsewhere that brought historians of science and philosophers together in unified programs.
• Science, technology, and society. In the mid-to-late-1960s, student and faculty social movements in the U.S., UK, and European universities helped to launch a range of new interdisciplinary fields (such as women's studies) that were seen to address relevant topics that the traditional curriculum ignored. One such development was the rise of "science, technology, and society" programs, which are also—confusingly—known by the STS acronym. Drawn from a variety of disciplines, including anthropology, history, political science, and sociology, scholars in these programs created undergraduate curricula devoted to exploring the issues raised by science and technology. Feminist scholars in this and other emerging STS areas addressed themselves to the exclusion of women from science and engineering, focusing instead on critiquing gendered power dynamics in prior STS research.
• Science, engineering, and public policy studies emerged in the 1970s from the same concerns that motivated the founders of the science, technology, and society movement: A sense that science and technology were developing in ways that were increasingly at odds with the public's best interests. The science, technology, and society movement tried to humanize those who would make tomorrow's science and technology, but this discipline took a different approach: It would train students with the professional skills needed to become players in science and technology policy. Some programs came to emphasize quantitative methodologies, and most of these were eventually absorbed into systems engineering. Others emphasized sociological and qualitative approaches, and found that their closest kin could be found among scholars in science, technology, and society departments.

During the 1970s and 1980s, universities in the US, UK, and Europe began drawing these various components together in new, interdisciplinary programs. For example, in the 1970s, Cornell University developed a new program that united science studies and policy-oriented scholars with historians and philosophers of science and technology. Each of these programs developed unique identities due to variations in the components that were drawn together, as well as their location within the various universities. For example, the University of Virginia's STS program united scholars drawn from a variety of fields (with particular strength in the history of technology); however, the program's teaching responsibilities—it is located within an engineering school and teaches ethics to undergraduate engineering students—means that all of its faculty share a strong interest in engineering ethics.

The "turn to technology" (and beyond)

See also: Social construction of technology

A decisive moment in the development of STS was the mid-1980s addition of technology studies to the range of interests reflected in science. During that decade, two works appeared en seriatim that signaled what Steve Woolgar was to call the "turn to technology". In a seminal 1984 article, Trevor Pinch and Wiebe Bijker showed how the sociology of technology could proceed along the theoretical and methodological lines established by the sociology of scientific knowledge. This was the intellectual foundation of the field they called the social construction of technology. Donald MacKenzie and Judy Wajcman primed the pump by publishing a collection of articles attesting to the influence of society on technological design (Social Shaping of Technology, 1985). Social science research continued to interrogate STS research from this point onward as researchers moved from post-modern to post-structural frameworks of thought, Bijker and Pinch contributing to SCOT knowledge and Wajcman providing boundary work through a feminist lens.

The "turn to technology" helped to cement an already growing awareness of underlying unity among the various emerging STS programs. More recently, there has been an associated turn to ecology, nature, and materiality in general, whereby the socio-technical and natural/material co-produce each other. This is especially evident in work in STS analyses of biomedicine (such as Carl May and Annemarie Mol) and ecological interventions (such as Bruno Latour, Sheila Jasanoff, Matthias Gross, Sara B. Pritchard, and S. Lochlann Jain). Ruth Schwartz Cowan has studied how gender and technology co-produce each other.

Important concepts

Social construction(s)

Main article: Social construction of technology

Social constructions are human-created ideas, objects, or events created by a series of choices and interactions. These interactions have consequences that change the perception that different groups of people have on these constructs. Some examples of social construction include class, race, money, and citizenship.

The following also alludes to the notion that not everything is set, a circumstance or result could potentially be one way or the other. According to the article "What is Social Construction?" by Ian Hacking, "Social construction work is critical of the status quo. Social constructionists about X tend to hold that:

1. X need not have existed, or need not be at all as it is. X, or X as it is at present, is not determined by the nature of things; it is not inevitable

Very often they go further, and urge that:

1. X is quite as bad as it is.
2. We would be much better off if X were done away with, or at least radically transformed."

In the past, there have been viewpoints that were widely regarded as fact until being called to question due to the introduction of new knowledge. Such viewpoints include the past concept of a correlation between intelligence and the nature of a human's ethnicity or race (X may not be at all as it is).

An example of the evolution and interaction of various social constructions within science and technology can be found in the development of both the high-wheel bicycle, or velocipede, and then of the bicycle. The velocipede was widely used in the latter half of the 19th century. In the latter half of the 19th century, a social need was first recognized for a more efficient and rapid means of transportation. Consequently, the velocipede was first developed, which was able to reach higher translational velocities than the smaller non-geared bicycles of the day, by replacing the front wheel with a larger radius wheel. One notable trade-off was a certain decreased stability leading to a greater risk of falling. This trade-off resulted in many riders getting into accidents by losing balance while riding the bicycle or being thrown over the handlebars.

The first "social construction" or progress of the velocipede caused the need for a newer "social construction" to be recognized and developed into a safer bicycle design. Consequently, the velocipede was then developed into what is now commonly known as the "bicycle" to fit within society's newer "social construction," the newer standards of higher vehicle safety. Thus the popularity of the modern geared bicycle design came as a response to the first social construction, the original need for greater speed, which had caused the high-wheel bicycle to be designed in the first place. The popularity of the modern geared bicycle design ultimately ended the widespread use of the velocipede itself, as eventually it was found to best accomplish the social needs/social constructions of both greater speed and of greater safety.

Material semiotics

See also: Feminist science and technology studies

With methodology from actor-network theory (ANT), feminist STS theorists built upon SCOT's theory of co-construction to explore the relationship between gender and technology, proposing one cannot exist separately from the other. This approach suggests the material and social are not separate, reality being produced through interactions and studied through representations of those realities. Building on Steve Woolgar's boundary work on user configuration, feminist critiques shifted the focus away from users of technology and science towards whether technology and science represent a fixed, unified reality. According to this approach, identity could no longer be treated as causal in human interactions with technology as it cannot exist prior to that interaction, feminist STS researchers proposing a "double-constructivist" approach to account for this contradiction. John Law credits feminist STS scholars for contributing material-semiotic approaches to the broader discipline of STS, stating that research not only attempts to describe reality, but enacts it through the research process.

Sociotechnical imaginaries (STIs)

Sociotechnical imaginaries are what certain communities, societies, and nations envision as achievable through the combination of scientific innovation and social changes. These visions can be based on what is possible to achieve for a certain society, and can also show what a certain state or nation desires. STIs are often bound with ideologies and ambitions of those who create and circulate them. Sociotechnical imaginaries can be created by states and policymakers, smaller groups within society, or can be a result of the interaction of both.

The term was coined in 2009 by Sheila Jasanoff and Sang-Hyun Kim who compared and contrasted sociotechnical imaginaries of nuclear energy in the USA with those of South Korea over the second half of the 20th century. Jasanoff and Kim analyzed the discourse of government representatives, national policies, and civil society organizations, looked at the technological and infrastructural developments, and social protests, and conducted interviews with experts. They concluded that in South Korea nuclear energy was imagined mostly as the means of national development, while in the US the dominant sociotechnical imaginary framed nuclear energy as risky and in need of containment.

The concept has been applied to several objects of study including biomedical research, nanotechnology development and energy systems and climate change. Within energy systems, research has focused on nuclear energy, fossil fuels, renewables as well as broader topics of energy transitions, and the development of new technologies to address climate change.

Sociotechnical systems theory

Main article: Sociotechnical system

Social technical systems are an interplay between technologies and humans, this is clearly expressed in the sociotechnical systems theory. To expound on this interplay, humans fulfill and define tasks, then humans in companies use IT and IT supports people, and finally, IT processes tasks and new IT generates new tasks. This IT redefines work practices. This is what we call the sociotechnical systems. In socio-technical systems, there are two principles to internalize, that is joint optimization and complementarity. Joint optimization puts an emphasis on developing both systems in parallel and it is only in the interaction of both systems that the success of an organization arises. The principle of complementarity means that both systems have to be optimized. If you focus on one system and have bias over the other it will likely lead to the failure of the organization or jeopardize the success of a system. Although the above socio-technical system theory is focused on an organization, it is undoubtedly imperative to correlate this theory and its principles to society today and in science and technology studies. Understanding technology in the context of national development: critical reflections discusses how governance frameworks, digital infrastructure, and institutional capacity influence the societal outcomes of technology adoption.

According to Barley and Bailey, there is a tendency for AI designers and scholars of design studies to privilege the technical over the social, focusing more on taking "humans out of the loop" paradigm than the "augmented intelligence" paradigm.

Recent work on artificial intelligence considers large sociotechnical systems, such as social networks and online marketplaces, as agents whose behavior can be purposeful and adaptive. The behavior of recommender systems can therefore be analyzed in the language and framework of sociotechnical systems, leading also to a new perspective for their legal regulation.

Technoscience

Main article: Technoscience

Technoscience is a subset of Science, Technology, and Society studies that focuses on the inseparable connection between science and technology. It states that fields are linked and grow together, and scientific knowledge requires an infrastructure of technology in order to remain stationary or move forward. Both technological development and scientific discovery drive one another towards more advancement. Technoscience excels at shaping human thoughts and behavior by opening up new possibilities that gradually or quickly come to be perceived as necessities.

Technosocial

"Technological action is a social process." Social factors and technology are intertwined so that they are dependent upon each other. This includes the aspect that social, political, and economic factors are inherent in technology and that social structure influences what technologies are pursued. In other words, "technoscientific phenomena combined inextricably with social/political/economic/psychological phenomena, so 'technology' includes a spectrum of artifacts, techniques, organizations, and systems." Winner expands on this idea by saying "in the late twentieth-century technology and society, technology and culture, technology and politics are by no means separate."

Examples

• Ford Pinto – Ford Motor Company sold and produced the Pinto during the 1970s. A flaw in the automobile design of the rear gas tank caused a fiery explosion upon impact. The exploding fuel tank killed and injured hundreds of people. Internal documents of test results proved Ford CEO Lee Iacocca and engineers were aware of the flaw. The company decided to ignore improving its technology because of profit-driven motives, strict internal control, and competition from foreign competitors such as Volkswagen. Ford Motor Company conducted a cost-benefit analysis to determine if altering the Ford Pinto model was feasible. An analysis conducted by Ford employees argued against a new design because of increased cost. Employees were also under tight control by the CEO who rushed the Pinto through production lines to increase profits. Ford finally changed after public scrutiny. Safety organizations later influenced this technology by requiring stricter safety standards for motor vehicles.
• DDT/toxins – DDT was a common and highly effective insecticide used during the 1940s until its ban in the early 1970s. It was utilized during World War 2 to combat insect-borne human diseases that plagued military members and civilian populations. People and companies soon realized other benefits of DDT for agricultural purposes. Rachel Carson became worried about widespread use on public health and the environment. Rachel Carson's book Silent Spring left an imprint on the industry by claiming the linkage of DDT to many serious illnesses such as cancer. Carson's book drew criticism from chemical companies who felt their reputation and business threatened by such claims. DDT was eventually banned by the United States Environmental Protection Agency (EPA) after a long and arduous process of research on the chemical substance. The main cause for the removal of DDT was the public deciding that any benefits were outweighed by the potential health risk.
• Autopilots/computer-aided tasks (CATs) – From a security point of view the effects of making a task more computer-driven is in the favor of technological advance because there is less reaction time required and computational error than a human pilot. Due to reduced error and reaction times flights on average, using autopilot, have been shown to be safer. Thus technology has a direct impact on people by increasing their safety, and society affects technology because people want to be safer so they are constantly trying to improve the autopilot systems.
• Cell phones – Cell phone technology emerged in the early 1920s after advancements were made in radio technology. Engineers at Bell Laboratories, the research, and development division of AT&T discovered that cell towers can transmit and receive signals to and from many directions. The discovery by Bell Labs revolutionized the capabilities and outcomes of cellular technology. Technology only improved once mobile phone users could communicate outside of a designated area. First-generation mobile phones were first created and sold by Motorola. Their phone was only intended for use in cars. Second-generation mobile phone capabilities continued to improve because of the switch to digital. Phones were faster which enhanced the communication capabilities of customers. They were also sleeker and weighed less than bulky first-generation technology. Technological advances boosted customer satisfaction and broadened cell phone companies' customer base. Third-generation technology changed the way people interact with others. Now customers had access to Wi-Fi, texting and other applications. Mobile phones are now entering into the fourth generation. Cellular and mobile phones revolutionized the way people socialize and communicate in order to establish a modern social structure. People have affected the development of this technology by demanding features such as larger screens, touch capabilities, and internet accessibility.
• Internet – The internet arose because of extensive research on ARPANET between various universities, corporations, and ARPA (Advanced Research Project Agency), an agency of the Department of Defense. Scientists theorized a network of computers connected to each other. Computing capabilities contributed to developments and the creation of the modern-day computer or laptop. The internet has become a normal part of life and business, to such a degree that the United Nations views it as a basic human right. The internet is becoming larger, one way is that more things are being moved into the digital world due to demand, for example, online banking. It has drastically changed the way most people go about daily habits.

Deliberative democracy

Deliberative democracy is a reform of representative or direct democracies which mandates discussion and debate of popular topics which affect society. Deliberative democracy is a tool for making decisions. Deliberative democracy can be traced back all the way to Aristotle's writings. More recently, the term was coined by Joseph Bessette in his 1980 work Deliberative Democracy: The Majority Principle in Republican Government, where he uses the idea in opposition to the elitist interpretations of the United States Constitution with emphasis on public discussion.

Deliberative democracy can lead to more legitimate, credible, and trustworthy outcomes. Deliberative democracy allows for "a wider range of public knowledge", and it has been argued that this can lead to "more socially intelligent and robust" science. One major shortcoming of deliberative democracy is that many models insufficiently ensure critical interaction.

According to Ryfe, there are five mechanisms that stand out as critical to the successful design of deliberative democracy:

• Rules of equality, civility, and inclusivity may prompt deliberation even when our first impulse is to avoid it.
• Stories anchor reality by organizing experience and instilling a normative commitment to civic identities and values, and function as a medium for framing discussions.
• Leadership provides important cues to individuals in deliberative settings and can keep groups on a deliberative track when their members slip into routine and habit.
• Individuals are more likely to sustain deliberative reasoning when they have a stake in the outcomes.
• Apprenticeship teaches citizens to deliberate well. We might do well to imagine education as a form of apprenticeship learning, in which individuals learn to deliberate by doing it in concert with others more skilled in the activity.

Importance

Recently, there has been a movement towards greater transparency in the fields of policy and technology. Jasanoff comes to the conclusion that there is no longer a question of if there needs to be increased public participation in making decisions about science and technology, but now there need to be ways to make a more meaningful conversation between the public and those developing the technology.

In practice

Bruce Ackerman and James S. Fishkin offered an example of a reform in their paper "Deliberation Day." The deliberation is to enhance public understanding of popular, complex and controversial issues through devices such as Fishkin's deliberative polling, though implementation of these reforms is unlikely in a large government such as that of the United States. However, things similar to this have been implemented in small, local governments like New England towns and villages. New England town hall meetings are a good example of deliberative democracy in a realistic setting.

An ideal deliberative democracy balances the voice and influence of all participants. While the main aim is to reach consensus, deliberative democracy should encourage the voices of those with opposing viewpoints, concerns due to uncertainties, and questions about assumptions made by other participants. It should take its time and ensure that those participating understand the topics on which they debate. Independent managers of debates should also have a substantial grasp of the concepts discussed, but must "[remain] independent and impartial as to the outcomes of the process."

Tragedy of the commons

See also: Tragedy of the commons

In 1968, Garrett Hardin popularised the phrase "tragedy of the commons." It is an economic theory where rational people act against the best interest of the group by consuming a common resource. Since then, the tragedy of the commons has been used to symbolize the degradation of the environment whenever many individuals use a common resource. Although Garrett Hardin was not an STS scholar, the concept of the tragedy of the commons still applies to science, technology, and society.

In a contemporary setting, the Internet acts as an example of the tragedy of the commons through the exploitation of digital resources and private information. Data and internet passwords can be stolen much more easily than physical documents. Virtual spying is almost free compared to the costs of physical spying. Additionally, net neutrality can be seen as an example of tragedy of the commons in an STS context. The movement for net neutrality argues that the Internet should not be a resource that is dominated by one particular group, specifically those with more money to spend on Internet access.

A counterexample to the tragedy of the commons is offered by Andrew Kahrl. Privatization can be a way to deal with the tragedy of the commons. However, Kahrl suggests that the privatization of beaches on Long Island, in an attempt to combat the overuse of Long Island beaches, made the residents of Long Island more susceptible to flood damage from Hurricane Sandy. The privatization of these beaches took away from the protection offered by the natural landscape. Tidal lands that offer natural protection were drained and developed. This attempt to combat the tragedy of the commons by privatization was counter-productive. Privatization actually destroyed the public good of natural protection from the landscape.

Alternative modernity

Alternative modernity is a conceptual tool conventionally used to represent the state of present western society. Modernity represents the political and social structures of society, the sum of interpersonal discourse, and ultimately a snapshot of society's direction at a point in time. Unfortunately, conventional modernity is incapable of modeling alternative directions for further growth within our society. Also, this concept is ineffective at analyzing similar but unique modern societies such as those found in the diverse cultures of the developing world. Problems can be summarized into two elements: inward failure to analyze the growth potentials of a given society, and outward failure to model different cultures and social structures and predict their growth potentials.

Previously, modernity carried a connotation of the current state of being modern, and its evolution through European colonialism. The process of becoming "modern" is believed to occur in a linear, pre-determined way, and is seen by Philip Brey as a way to interpret and evaluate social and cultural formations. This thought ties in with modernization theory, the thought that societies progress from "pre-modern" to "modern" societies.

Within the field of science and technology, there are two main lenses with which to view modernity. The first is as a way for society to quantify what it wants to move towards. In effect, we can discuss the notion of "alternative modernity" (as described by Andrew Feenberg) and which of these we would like to move towards. Alternatively, modernity can be used to analyze the differences in interactions between cultures and individuals. From this perspective, alternative modernities exist simultaneously, based on differing cultural and societal expectations of how a society (or an individual within society) should function. Because of different types of interactions across different cultures, each culture will have a different modernity.

Pace of innovation

See also: Pace of innovation

The pace of innovation is the speed at which technological innovation or advancement is occurring, with the most apparent instances being too slow or too rapid. Both these rates of innovation are extreme and therefore have effects on the people that get to use this technology.

No innovation without representation

Main article: No innovation without representation

"No innovation without representation" is a democratic ideal of ensuring that everyone involved gets a chance to be represented fairly in technological developments.

• Langdon Winner states that groups and social interests likely to be affected by a particular kind of technological change ought to be represented at an early stage in defining exactly what that technology will be. It is the idea that relevant parties have a say in technological developments and are not left in the dark.
• Spoken about by Massimiano Bucchi
• This ideal does not require the public to become experts on the topics of science and engineering, it only asks that the opinions and ideas be heard before making drastic decisions, as talked about by Steven L. Goldman.

Legacy thinking

Legacy thinking is defined as an inherited method of thinking imposed from an external source without objection by the individual because it is already widely accepted by society.

Legacy thinking can impair the ability to drive technology for the betterment of society by blinding people to innovations that do not fit into their accepted model of how society works. By accepting ideas without questioning them, people often see all solutions that contradict these accepted ideas as impossible or impractical. Legacy thinking tends to advantage the wealthy, who have the means to project their ideas on the public. It may be used by the wealthy as a vehicle to drive technology in their favor rather than for the greater good. Examining the role of citizen participation and representation in politics provides an excellent example of legacy thinking in society. The belief that one can spend money freely to gain influence has been popularized, leading to public acceptance of corporate lobbying. As a result, a self-established role in politics has been cemented where the public does not exercise the power ensured to them by the Constitution to the fullest extent. This can become a barrier to political progress as corporations who have the capital to spend have the potential to wield great influence over policy. Legacy thinking, however, keeps the population from acting to change this, despite polls from Harris Interactive that report over 80% of Americans to feel that big business holds too much power in government. Therefore, Americans are beginning to try to steer away from this line of thought, rejecting legacy thinking, and demanding less corporate, and more public, participation in political decision-making.

Additionally, an examination of net neutrality functions as a separate example of legacy thinking. Starting with dial-up, the internet has always been viewed as a private luxury good. Internet today is a vital part of modern-day society members. They use it in and out of life every day. Corporations are able to mislabel and greatly overcharge for their internet resources. Since the American public is so dependent upon the internet there is little for them to do. Legacy thinking has kept this pattern on track despite growing movements arguing that the internet should be considered a utility. Legacy thinking prevents progress because it was widely accepted by others before us through advertising that the internet is a luxury and not a utility. Due to pressure from grassroots movements the Federal Communications Commission (FCC) has redefined the requirements for broadband and internet in general as a utility. Now AT&T and other major internet providers are lobbying against this action and are in large able to delay the onset of this movement due to legacy thinking's grip on American culture and politics.

For example, those who cannot overcome the barrier of legacy thinking may not consider the privatization of clean drinking water as an issue. This is partial because access to water has become such a given fact of the matter to them. For a person living in such circumstances, it may be widely accepted to not concern themselves with drinking water because they have not needed to be concerned with it in the past. Additionally, a person living within an area that does not need to worry about their water supply or the sanitation of their water supply is less likely to be concerned with the privatization of water.

This notion can be examined through the thought experiment of "veil of ignorance". Legacy thinking causes people to be particularly ignorant about the implications behind the "you get what you pay for" mentality applied to a life necessity. By utilizing the "veil of ignorance", one can overcome the barrier of legacy thinking as it requires a person to imagine that they are unaware of their own circumstances, allowing them to free themselves from externally imposed thoughts or widely accepted ideas.

Related concepts

• Technoscience – The perception that science and technology are intertwined and depend on each other.
• Technosociety – An industrially developed society with a reliance on technology.
• Technological utopianism – A positive outlook on the effect technology has on social welfare. Includes the perception that technology will one day enable society to reach a utopian state.
• Technosocial systems – people and technologies that combine to work as heterogeneous but functional wholes.
• Critical Technical Practice – the practice of technological creation while simultaneously critiquing and maintaining awareness of the inherent biases and value systems which become embedded in those technologies.

Classifications

• Technological optimism – The opinion that technology has positive effects on society and should be used in order to improve the welfare of people.
• Technological pessimism – The opinion that technology has negative effects on society and should be discouraged from use.
• Technological neutrality – "maintains that a given technology has no systematic effects on society: individuals are perceived as ultimately responsible, for better or worse, because technologies are merely tools people use for their own ends."
• Technological determinism – "maintains that technologies are understood as simply and directly causing particular societal outcomes."
• Scientism – The belief in the total separation of facts and values.
• Technological progressivism – technology is a means to an end itself and an inherently positive pursuit.

Academic programs

STS is taught in several countries. According to the STS wiki, STS programs can be found in twenty countries, including 45 programs in the United States, three programs in India, and eleven programs in the UK. STS programs can be found in Canada, Germany, Israel, Malaysia, and Taiwan. Some examples of institutions offering STS programs are Stanford University, University College London, Harvard University, the University of Oxford, Mines ParisTech, Bar-Ilan University, and York University. In Europe the European Inter-University Association on Society, Science and Technology (ESST) offers an MA degree in STS through study programs and student exchanges with over a dozen specializations.

Professional associations

The field has professional associations in regions and countries around the world.

In Europe

• In Europe, the European Association for the Study of Science and Technology (EASST) was founded in 1981 to "improve scholarly communication and exchange in the field", "increase the visibility of the subject to policy-makers and to the general public", and "stimulate and support teaching on the subject at all levels". Similarly, the European Inter-University Association on Society, Science and Technology (ESST) researches and studies science and technology in society, in both historical and contemporary perspectives.
• In European nation states and language communities, a range of STS associations exist, including in the UK, Spain, Germany, Austria, Turkey. In some states, several formal associations exist.
  • For instance, in 2015, the UK-based Association for Studies in Innovation, Science and Technology (AsSIST-UK) was established, chaired by Andrew Webster (York) and Robin Williams (Edinburgh) principally to foster stronger integration between the innovation studies and STS fields. In 2021 it had a membership of 380. It holds annual conferences and has built strong links to policy practitioners in Westminster.
  • In Italy, STS Italia – The Italian Society for Social Studies of Science and Technology was founded in 2005. Its mission is "to build up an Italian network of researchers oriented to study Science and Technology starting from the social dynamics which characterize and interweave science and technology themselves".
  • In Sweden, the Swedish Network for Science and Technology Studies was founded in 2006, at the first national Swedish Conference for STS, STS Dagarna.
  • In Germany several STS associations exist, including the Gesellschaft für Wissenschafts- und Technikforschung, founded in 1987 or the stsing network, labelled "Doing Science and Technology Studies in and through Germany", founded 2020, an early career research network called INSIST and various STS-related sub-groups of the larger disciplinary associations (like sociology).

In Asia

• The Asia Pacific Science Technology & Society Network (APSTSN) primarily had members from Australasia, Southeast and East Asia and Oceania. APSTSN is not currently active.
• In Japan, the Japanese Society for Science and Technology Studies (JSSTS) was founded in 2001.
• The Australasian Science and Technology Studies Network (AusSTS) was founded in 2017 based at Deakin University. AusSTS now has several nodes in Australia and Aotearoa New Zealand and holds an annual workshop.
• In India, the Science and Technology Studies-India Network (STS-IN) was formed in December 2023. The Inaugural workshop was held on December 14 and 15, 2023, at Indian Institute of Technology Hyderabad.

In Latin America

• Estudios Sociales de la Ciencia y la Tecnología (ESOCITE) is the biggest association of Science and Technology studies. The study of STS (CyT in Spanish, CTS in Portuguese) here was shaped by authors like Amílcar Herrera [es] and Jorge Sabato and Oscar Varsavsky [es] in Argentina, José Leite Lopes in Brazil, Miguel Wionczek in Mexico, Francisco Sagasti in Peru, Máximo Halty Carrere in Uruguay and Marcel Roche in Venezuela.

In North America

• Founded in 1975, the Society for Social Studies of Science initially provided scholarly communication facilities, including a journal (Science, Technology, and Human Values) and annual meetings that were mainly attended by science studies scholars. The society has since grown into the most important professional association of science and technology studies scholars worldwide. The Society for Social Studies of Science members also include government and industry officials concerned with research and development as well as science and technology policy; scientists and engineers who wish to better understand the social embeddedness of their professional practice; and citizens concerned about the impact of science and technology in their lives.
• Founded in 1958, the Society for the History of Technology initially attracted members from the history profession who had interests in the contextual history of technology. After the "turn to technology" in the mid-1980s, the society's well-regarded journal (Technology and Culture) and its annual meetings began to attract considerable interest from non-historians with technology studies interests.
• Less identified with STS, but also of importance to many STS scholars, are the History of Science Society, the Philosophy of Science Association, and the American Association for the History of Medicine.
• Additionally, within the US there are significant STS-oriented special interest groups within major disciplinary associations, including the American Anthropological Association, the American Political Science Association, the National Women's Studies Association, and the American Sociological Association.

Flash memory

From Wikipedia, the free encyclopedia

https://en.wikipedia.org/wiki/Flash_memory

A disassembled USB flash drive in 2005. The chip on the left is flash memory. The Silicon Motion controller is on the right.

Flash memory is an electronic non-volatile computer memory storage medium that can be electrically erased and reprogrammed. The two main types of flash memory, NOR flash and NAND flash, are named for the NOR and NAND logic gates. Both use the same cell design, consisting of floating-gate MOSFETs. They differ at the circuit level, depending on whether the state of the bit line or word lines is pulled high or low; in NAND flash, the relationship between the bit line and the word lines resembles a NAND gate; in NOR flash, it resembles a NOR gate.

Flash memory, a type of floating-gate memory, was invented by Fujio Masuoka at Toshiba in 1980 and is based on EEPROM technology. Toshiba began marketing flash memory in 1987. EPROMs had to be erased completely before they could be rewritten. NAND flash memory, however, may be erased, written, and read in blocks (or pages), which generally are much smaller than the entire device. NOR flash memory allows a single machine word to be written – to an erased location – or read independently. A flash memory device typically consists of one or more flash memory chips (each holding many flash memory cells), along with a separate flash memory controller chip.

The NAND type is found mainly in memory cards, USB flash drives, solid-state drives (those produced since 2009), feature phones, smartphones, and similar products, for general storage and transfer of data. NAND or NOR flash memory is also often used to store configuration data in digital products, a task previously made possible by EEPROM or battery-powered static RAM. A key disadvantage of flash memory is that it can endure only a relatively small number of write cycles in a specific block.

NOR flash is known for its direct random-access capabilities, making it apt for executing code directly. Its architecture allows for individual byte access, facilitating faster read speeds compared to NAND flash. NAND flash memory operates with a different architecture, relying on a serial access approach. This makes NAND suitable for high-density data storage, but less efficient for random-access tasks. NAND flash is often employed in scenarios where cost-effective, high-capacity storage is crucial, such as in USB drives, memory cards, and solid-state drives (SSDs).

The primary differentiator lies in their use cases and internal structures. NOR flash is optimal for applications requiring quick access to individual bytes, as in embedded systems for program execution. NAND flash, on the other hand, shines in scenarios demanding cost-effective, high-capacity storage with sequential data access.

Flash memory is used in computers, PDAs, digital audio players, digital cameras, mobile phones, synthesizers, video games, scientific instrumentation, industrial robotics, and medical electronics. Flash memory has a fast read access time but is not as fast as static RAM or ROM. In portable devices, it is preferred to use flash memory because of its mechanical shock resistance, since mechanical drives are more prone to mechanical damage.

Because erase cycles are slow, the large block sizes used in flash memory erasing give it a significant speed advantage over non-flash EEPROM when writing large amounts of data. As of 2019, flash memory costs much less than byte-programmable EEPROM and has become the dominant memory type wherever a system required a significant amount of non-volatile solid-state storage. EEPROMs, however, are still used in applications that require only small amounts of storage, e.g. in SPD implementations on computer-memory modules.

Flash memory packages can use die stacking with through-silicon vias and several dozen layers of 3D TLC NAND cells (per die) simultaneously to achieve capacities of up to 1 tebibyte per package using 16 stacked dies and an integrated flash controller as a separate die inside the package.

History

Background

The origins of flash memory can be traced to the development of the floating-gate MOSFET (FGMOS), also known as the floating-gate transistor. The original MOSFET was invented at Bell Labs between 1959 and 1960. Dawon Kahng went on to develop a variation, the floating-gate MOSFET, with Taiwanese-American engineer Simon Min Sze at Bell Labs in 1967. They proposed that it could be used as floating-gate memory cells for storing a form of programmable read-only memory (PROM) that is both non-volatile and re-programmable.

Early types of floating-gate memory included EPROM (erasable PROM) and EEPROM (electrically erasable PROM) in the 1970s. However, early floating-gate memory required engineers to build a memory cell for each bit of data, which proved to be cumbersome, slow, and expensive, restricting floating-gate memory to niche applications in the 1970s, such as military equipment and the earliest experimental mobile phones.

Modern EEPROM based on Fowler-Nordheim tunnelling to erase data was invented by Bernward and patented by Siemens in 1974. It was further developed between 1976 and 1978 by Eliyahou Harari at Hughes Aircraft Company, as well as by George Perlegos and others at Intel.

Invention and commercialization

Fujio Masuoka invented flash memory at Toshiba in 1980. The improvement between EEPROM and flash is that flash is programmed in blocks while EEPROM is programmed in bytes. According to Toshiba, the name "flash" was suggested by Masuoka's colleague, Shōji Ariizumi, because the erasure process of the memory contents reminded him of the flash of a camera. Masuoka and colleagues presented the invention of NOR flash in 1984, and then NAND flash at the IEEE 1987 International Electron Devices Meeting (IEDM) held in San Francisco.

Toshiba commercially launched NAND flash memory in 1987. Intel Corporation introduced the first commercial NOR type flash chip in 1988. NOR-based flash has long erase and write times, but provides full address and data buses, allowing random access to any memory location. This makes it a suitable replacement for older read-only memory (ROM) chips, which are used to store program code that rarely needs to be updated, such as a computer's BIOS or the firmware of set-top boxes. Its endurance may be from as little as 100 erase cycles for an on-chip flash memory, to a more typical 10,000 or 100,000 erase cycles, up to 1,000,000 erase cycles. NOR-based flash was the basis of early flash-based removable media; CompactFlash was originally based on it, although later cards moved to less expensive NAND flash.

NAND flash has reduced erase and write times, and requires less chip area per cell, thus allowing greater storage density and lower cost per bit than NOR flash. However, the I/O interface of NAND flash does not provide a random-access external address bus. Rather, data must be read on a block-wise basis, with typical block sizes of hundreds to thousands of bits. This makes NAND flash unsuitable as a drop-in replacement for program ROM, since most microprocessors and microcontrollers require byte-level random access. In this regard, NAND flash is similar to other secondary data storage devices, such as hard disks and optical media, and is thus highly suitable for use in mass-storage devices, such as memory cards and solid-state drives (SSD). For example, SSDs store data using multiple NAND flash memory chips.

The first NAND-based removable memory card format was SmartMedia, released in 1995. Many others followed, including MultiMediaCard, Secure Digital, Memory Stick, and xD-Picture Card.

Later developments

A new generation of memory card formats, including RS-MMC, miniSD and microSD, feature extremely small form factors. For example, the microSD card has an area of just over 1.5 cm², with a thickness of less than 1 mm.

NAND flash has achieved significant levels of memory density as a result of several major technologies that were commercialized during the late 2000s to early 2010s.

NOR flash was the most common type of Flash memory sold until 2005, when NAND flash overtook NOR flash in sales.

Multi-level cell (MLC) technology stores more than one bit in each memory cell. NEC demonstrated multi-level cell (MLC) technology in 1998, with an 80 Mb flash memory chip storing 2 bits per cell. STMicroelectronics also demonstrated MLC in 2000, with a 64 MB NOR flash memory chip. In 2009, Toshiba and SanDisk introduced NAND flash chips with QLC technology storing 4 bits per cell and holding a capacity of 64 Gb. Samsung Electronics introduced triple-level cell (TLC) technology storing 3-bits per cell, and began mass-producing NAND chips with TLC technology in 2010.

Charge trap flash

Main article: Charge trap flash

Charge trap flash (CTF) technology replaces the polysilicon floating gate, which is sandwiched between a blocking gate oxide above and a tunneling oxide below it, with an electrically insulating silicon nitride layer; the silicon nitride layer traps electrons. In theory, CTF is less prone to electron leakage, providing improved data retention.

Because CTF replaces the polysilicon with an electrically insulating nitride, it allows for smaller cells and higher endurance (lower degradation or wear). However, electrons can become trapped and accumulate in the nitride, leading to degradation. Leakage is exacerbated at high temperatures since electrons become more excited with increasing temperatures. CTF technology, however, still uses a tunneling oxide and blocking layer, which are the weak points of the technology, since they can still be damaged in the usual ways (the tunnel oxide can be degraded due to extremely high electric fields and the blocking layer due to Anode Hot Hole Injection (AHHI).

Degradation or wear of the oxides is the reason why flash memory has limited endurance. Data retention goes down (the potential for data loss increases) with increasing degradation, since the oxides lose their electrically-insulating characteristics as they degrade. The oxides must insulate against electrons to prevent them from leaking, which would cause data loss.

In 1991, NEC researchers, including N. Kodama, K. Oyama and Hiroki Shirai, described a type of flash memory with a charge-trap method. In 1998, Boaz Eitan of Saifun Semiconductors (later acquired by Spansion) patented a flash memory technology named NROM that took advantage of a charge trapping layer to replace the conventional floating gate used in conventional flash memory designs. In 2000, an Advanced Micro Devices (AMD) research team led by Richard M. Fastow, Egyptian engineer Khaled Z. Ahmed and Jordanian engineer Sameer Haddad (who later joined Spansion) demonstrated a charge-trapping mechanism for NOR flash memory cells. CTF was later commercialized by AMD and Fujitsu in 2002. 3D V-NAND (vertical NAND) technology stacks NAND flash memory cells vertically within a chip using 3D charge trap flash (CTP) technology. 3D V-NAND technology was first announced by Toshiba in 2007, and the first device, with 24 layers, was commercialized by Samsung Electronics in 2013.

3D integrated circuit technology

3D integrated circuit (3D IC) technology stacks integrated circuit (IC) chips vertically into a single 3D IC package. Toshiba introduced 3D IC technology to NAND flash memory in April 2007, when they debuted a 16 GB eMMC compliant (product number THGAM0G7D8DBAI6, often abbreviated THGAM on consumer websites) embedded NAND flash memory package, which was manufactured with eight stacked 2 GB NAND flash chips. In September 2007, Hynix Semiconductor (now SK Hynix) introduced 24-layer 3D IC technology, with a 16 GB flash memory package that was manufactured with 24 stacked NAND flash chips using a wafer bonding process. Toshiba also used an eight-layer 3D IC for their 32 GB THGBM flash package and in 2008. In 2010, Toshiba used a 16-layer 3D IC for their 128 GB THGBM2 flash package, which was manufactured with 16 stacked 8 GB chips. In the 2010s, 3D ICs came into widespread commercial use for NAND flash memory in mobile devices.

In 2016, Micron and Intel introduced a technology known as CMOS Under the Array/CMOS Under Array (CUA), Core over Periphery (COP), Periphery Under Cell (PUA), or Xtacking, in which the control circuitry for the flash memory is placed under or above the flash memory cell array. This has allowed for an increase in the number of planes or sections a flash memory chip has, increasing from two planes to four, without increasing the area dedicated to the control or periphery circuitry. This increases the number of IO operations per flash chip or die, but it also introduces challenges when building capacitors for charge pumps used to write to the flash memory. Some flash dies have as many as 6 planes.

As of August 2017, microSD cards with a capacity up to 400 GB (400 billion bytes) were available. Samsung combined 3D IC chip stacking with its 3D V-NAND and TLC technologies to manufacture its 512 GB KLUFG8R1EM flash memory package with eight stacked 64-layer V-NAND chips. In 2019, Samsung produced a 1024 GB flash package, with eight stacked 96-layer V-NAND package and with QLC technology.

In 2025, researchers announced experimental success with a device having a 400-picosecond write time.

Principles of operation

A flash memory cell

Flash memory stores information in an array of memory cells made from floating-gate transistors. In single-level cell (SLC) devices, each cell stores only one bit of information. Multi-level cell (MLC) devices, including triple-level cell (TLC) devices, can store more than one bit per cell.

The floating gate may be conductive (typically polysilicon in most kinds of flash memory) or non-conductive (as in SONOS flash memory).

Floating-gate MOSFET

Main article: Floating-gate MOSFET

In flash memory, each memory cell resembles a standard metal–oxide–semiconductor field-effect transistor (MOSFET) except that the transistor has two gates instead of one. The cells can be seen as an electrical switch in which current flows between two terminals (source and drain) and is controlled by a floating gate (FG) and a control gate (CG). The CG is similar to the gate in other MOS transistors, but below this is the FG, which is insulated all around by an oxide layer. The FG is interposed between the CG and the MOSFET channel. Because the FG is electrically isolated by its insulating layer, electrons placed on it are trapped. When the FG is charged with electrons, this charge screens the electric field from the CG, thus increasing the threshold voltage (V_T) of the cell. This means that the V_T of the cell can be changed between the uncharged FG threshold voltage (V_T1) and the higher charged FG threshold voltage (V_T2) by changing the FG charge. In order to read a value from the cell, an intermediate voltage (V_I) between V_T1 and V_T2 is applied to the CG. If the channel conducts at V_I, the FG must be uncharged (if it were charged, there would not be conduction because V_I is less than V_T2). If the channel does not conduct at the V_I, it indicates that the FG is charged. The binary value of the cell is sensed by determining whether there is current flowing through the transistor when V_I is asserted on the CG. In a multi-level cell device, which stores more than one bit per cell, the amount of current flow is sensed (rather than simply its presence or absence), in order to determine more precisely the level of charge on the FG.

Floating gate MOSFETs are so named because there is an electrically insulating tunnel oxide layer between the floating gate and the silicon, so the gate "floats" above the silicon. The oxide keeps the electrons confined to the floating gate. Degradation or wear (and the limited endurance of floating gate Flash memory) occurs due to the extremely high electric field (10 million volts per centimeter) experienced by the oxide. Such high voltage densities can break atomic bonds over time in the relatively thin oxide, gradually degrading its electrically insulating properties and allowing electrons to be trapped in and pass through freely (leak) from the floating gate into the oxide, increasing the likelihood of data loss since the electrons (the quantity of which is used to represent different charge levels, each assigned to a different combination of bits in MLC Flash) are normally in the floating gate. This is why data retention goes down and the risk of data loss increases with increasing degradation. The silicon oxide in a cell degrades with every erase operation. The degradation increases the amount of negative charge in the cell over time due to trapped electrons in the oxide and negates some of the control gate voltage. Over time, this also makes erasing the cell slower; to maintain the performance and reliability of the NAND chip, the cell must be retired from use. Endurance also decreases with the number of bits in a cell. With more bits in a cell, the number of possible states (each represented by a different voltage level) in a cell increases and is more sensitive to the voltages used for programming. Voltages may be adjusted to compensate for degradation of the silicon oxide, and as the number of bits increases, the number of possible states also increases and thus the cell is less tolerant of adjustments to programming voltages, because there is less space between the voltage levels that define each state in a cell.

Fowler–Nordheim tunneling

Main article: Fowler–Nordheim tunneling

The process of moving electrons from the control gate and into the floating gate is called Fowler–Nordheim tunneling, and it fundamentally changes the characteristics of the cell by increasing the MOSFET's threshold voltage. This, in turn, changes the drain-source current that flows through the transistor for a given gate voltage, which is ultimately used to encode a binary value. The Fowler-Nordheim tunneling effect is reversible, so electrons can be added to or removed from the floating gate, processes traditionally known as writing and erasing.

Internal charge pumps

Despite the need for relatively high programming and erasing voltages, virtually all flash chips today require only a single supply voltage and produce the high voltages that are required using on-chip charge pumps.

Over half the energy used by a 1.8 V-NAND flash chip is lost in the charge pump itself. Since boost converters are inherently more efficient than charge pumps, researchers developing low-power SSDs have proposed returning to the dual Vcc/Vpp supply voltages used on all early flash chips, driving the high Vpp voltage for all flash chips in an SSD with a single shared external boost converter.

In spacecraft and other high-radiation environments, the on-chip charge pump is the first part of the flash chip to fail, although flash memories will continue to work – in read-only mode – at much higher radiation levels.

NOR flash

NOR flash memory wiring and structure on silicon

In both NOR and NAND flash memories, the cells are arranged in a grid. We can think of the memory as consisting of "words" of a certain number of bits (or cells), with each word being confined to a particular column of the grid, and the bits being in different rows. All the bits of a particular word are linked by a wordline, a conductor connecting to the control gates of all the bits of that word. All the first bits of a certain number of adjacent words (columns) are linked by a bitline, as are all the second bits and so on. The bitlines connect to one of the terminals (source or drain) of the cells. By manipulating the voltages on the wordlines one can read a certain bit by measuring the voltage on the corresponding bitline. The way to do this depends on whether the memory chip is a NOR or a NAND flash.

In NOR flash, each cell has one end connected directly to ground, and the other end connected directly to a bit line. This arrangement is called "NOR flash" because it acts like a NOR gate  – if any of the word lines (connected to the CG of the cells) is brought high, the corresponding storage transistor may act to pull the output bit line low, but this depends on the charge in the floating gate. Since several words are connected by the bit line, the output does not depend on only two (the bitline staying high if neither the first NOR the second wordline is high) but on all (the bitline remaining high if NONE of the wordlines is high). So to read a bit of a certain word, all the wordlines except that of the desired word are put low.

NOR flash continues to be the technology of choice for embedded applications requiring a discrete non-volatile memory device.^{[citation needed]} The low read latencies characteristic of NOR devices allow for both direct code execution and data storage in a single memory product.

Programming

Programming a NOR memory cell (setting it to logical 0), via hot-electron injection

Erasing a NOR memory cell (setting it to logical 1), via quantum tunneling

A single-level NOR flash cell in its default state is logically equivalent to a binary "1" value, because current will flow through the channel under application of an appropriate voltage to the control gate, so that the bitline voltage is pulled down. A NOR flash cell can be programmed, or set to a binary "0" value, by the following procedure:

• an elevated on-voltage (typically >5 V) is applied to the CG
• the channel is now turned on, so electrons can flow from the source to the drain (assuming an NMOS transistor)
• the source-drain current is sufficiently high to cause some high energy electrons to jump through the insulating layer onto the FG, via a process called hot-electron injection.

Erasing

To erase a NOR flash cell (resetting it to the "1" state), a large voltage of the opposite polarity is applied between the CG and source terminal, pulling the electrons off the FG through Fowler–Nordheim tunneling (FN tunneling). This is known as Negative gate source erase. Newer NOR memories can erase using negative gate channel erase, which biases the wordline on a NOR memory cell block and the P-well of the memory cell block to allow FN tunneling to be carried out, erasing the cell block. Older memories used source erase, in which a high voltage was applied to the source and then electrons from the FG were moved to the source. Modern NOR flash memory chips are divided into erase segments (often called blocks or sectors). The erase operation can be performed only on a block-wise basis; all the cells in an erase segment must be erased together. Programming of NOR cells, however, generally can be performed one byte or word at a time.

NAND flash memory wiring and structure on silicon

NAND flash

NAND flash also uses a grid of floating-gate transistors (see above), but they are connected in a way that resembles a NAND gate: the transistors corresponding to a given bit of several words are connected in series, and the bitline is pulled low if all the word lines are pulled high (above the transistors' V_T). To read the bit of a particular word, its wordline is put low and all the other wordlines are put high, and then the bitline will reflect the state of the floating gate of the desired cell. These groups are then connected via some additional transistors to a NOR-style bit line array in the same way that single transistors are linked in NOR flash.

Compared to NOR flash, replacing single transistors with serial-linked groups adds an extra level of addressing. Whereas NOR flash might address memory by page then word, NAND flash might address it by page, word and bit. Bit-level addressing suits bit-serial applications (such as hard disk emulation), which access only one bit at a time. Execute-in-place applications, on the other hand, require every bit in a word to be accessed simultaneously. This requires word-level addressing. In any case, both bit and word addressing modes are possible with either NOR or NAND flash.

To read data, first the desired group is selected (in the same way that a single transistor is selected from a NOR array). Next, most of the word lines are pulled up above V_T2, while one of them is pulled up to V_I. The series group will conduct (and pull the bit line low) if the selected bit has not been programmed.

Despite the additional transistors, the reduction in ground wires and bit lines allows a denser layout and greater storage capacity per chip. (The ground wires and bit lines are actually much wider than the lines in the diagrams.) In addition, NAND flash is typically permitted to contain a certain number of faults (NOR flash, as is used for a BIOS ROM, is expected to be fault-free). Manufacturers try to maximize the amount of usable storage by shrinking the size of the transistors or cells, however the industry can avoid this and achieve higher storage densities per die by using 3D NAND, which stacks cells on top of each other.

NAND flash cells are read by analysing their response to various voltages.

Writing and erasing

NAND flash uses tunnel injection for writing and tunnel release for erasing. NAND flash memory forms the core of the removable USB storage devices known as USB flash drives, as well as most memory card formats and solid-state drives available today.

The hierarchical structure of NAND flash starts at a cell level which establishes strings, then pages, blocks, planes and ultimately a die. A string is a series of connected NAND cells in which the source of one cell is connected to the drain of the next one. Depending on the NAND technology, a string typically consists of 32 to 128 NAND cells. Strings are organised into pages which are then organised into blocks in which each string is connected to a separate line called a bitline. All cells with the same position in the string are connected through the control gates by a wordline. A plane contains a certain number of blocks that are connected through the same bitline. A flash die consists of one or more planes, and the peripheral circuitry that is needed to perform all the read, write, and erase operations.

The architecture of NAND flash means that data can be read and programmed (written) in pages, typically between 4 KiB and 16 KiB in size, but can only be erased at the level of entire blocks consisting of multiple pages. When a block is erased, all the cells are logically set to 1. Data can only be programmed in one pass to a page in a block that was erased. The programming process is set one or more cells from 1 to 0. Any cells that have been set to 0 by programming can only be reset to 1 by erasing the entire block. This means that before new data can be programmed into a page that already contains data, the current contents of the page plus the new data must all be copied to a new, erased page. If a suitable erased page is available, the data can be written to it immediately. If no erased page is available, a block must be erased before copying the data to a page in that block. The old page is then marked as invalid and is available for erasing and reuse. This is different from operating system LBA view, for example, if operating system writes 1100 0011 to the flash storage device (such as SSD), the data actually written to the flash memory may be 0011 1100.

Vertical NAND

3D NAND continues scaling beyond 2D.

Vertical NAND (V-NAND) or 3D NAND memory stacks memory cells vertically and uses a charge trap flash architecture. The vertical layers allow larger areal bit densities without requiring smaller individual cells. It is also sold under the trademark BiCS Flash, which is a trademark of Kioxia Corporation (formerly Toshiba Memory Corporation). 3D NAND was first announced by Toshiba in 2007. V-NAND was first commercially manufactured by Samsung Electronics in 2013.

Structure

V-NAND uses a charge trap flash geometry (which was commercially introduced in 2002 by AMD and Fujitsu) that stores charge on an embedded silicon nitride film. Such a film is more robust against point defects and can be made thicker to hold larger numbers of electrons. V-NAND wraps a planar charge trap cell into a cylindrical form. As of 2020, 3D NAND flash memories by Micron and Intel instead use floating gates, however, Micron 128 layer and above 3D NAND memories use a conventional charge trap structure, due to the dissolution of the partnership between Micron and Intel. Charge trap 3D NAND flash is thinner than floating gate 3D NAND. In floating gate 3D NAND, the memory cells are completely separated from one another, whereas in charge trap 3D NAND, vertical groups of memory cells share the same silicon nitride material.

An individual memory cell is made up of one planar polysilicon layer containing a hole filled by multiple concentric vertical cylinders. The hole's polysilicon surface acts as the gate electrode. The outermost silicon dioxide cylinder acts as the gate dielectric, enclosing a silicon nitride cylinder that stores charge, in turn enclosing a silicon dioxide cylinder as the tunnel dielectric that surrounds a central rod of conducting polysilicon which acts as the conducting channel.

Memory cells in different vertical layers do not interfere with each other, as the charges cannot move vertically through the silicon nitride storage medium, and the electric fields associated with the gates are closely confined within each layer. The vertical collection is electrically identical to the serial-linked groups in which conventional NAND flash memory is configured. There is also string stacking, which builds several 3D NAND memory arrays or "plugs" separately, but stacked together to create a product with a higher number of 3D NAND layers on a single die. Often, two or 3 arrays are stacked. The misalignment between plugs is in the order of 30 to 10nm.

Construction

Growth of a group of V-NAND cells begins with an alternating stack of conducting (doped) polysilicon layers and insulating silicon dioxide layers.

The next step is to form a cylindrical hole through these layers. In practice, a 128 Gbit V-NAND chip with 24 layers of memory cells requires about 2.9 billion such holes. Next, the hole's inner surface receives multiple coatings, first silicon dioxide, then silicon nitride, then a second layer of silicon dioxide. Finally, the hole is filled with conducting (doped) polysilicon.

Performance

As of 2013, V-NAND flash architecture allows read and write operations twice as fast as conventional NAND and can last up to 10 times as long, while consuming 50 percent less power. They offer comparable physical bit density using 10-nm lithography but may be able to increase bit density by up to two orders of magnitude, given V-NAND's use of up to several hundred layers. As of 2020, V-NAND chips with 160 layers are under development by Samsung. As the number of layers increases, the capacity and endurance of flash memory may be increased.

Cost

Minimum bit cost of 3D NAND from non-vertical sidewall. The top opening widens with more layers, counteracting the increase in bit density.

The wafer cost of a 3D NAND is comparable with scaled down (32 nm or less) planar NAND flash. However, with planar NAND scaling stopping at 16 nm, the cost per bit reduction can continue by 3D NAND starting with 16 layers. However, due to the non-vertical sidewall of the hole etched through the layers; even a slight deviation leads to a minimum bit cost, i.e., minimum equivalent design rule (or maximum density), for a given number of layers; this minimum bit cost layer number decreases for smaller hole diameter.

Limitations

Block erasure

One limitation of flash memory is that it can be erased only a block at a time. This generally sets all bits in the block to 1. Starting with a freshly erased block, any location within that block can be programmed. However, once a bit has been set to 0, only by erasing the entire block can it be changed back to 1. In other words, flash memory (specifically NOR flash) offers random-access read and programming operations but does not offer arbitrary random-access rewrite or erase operations. A location can, however, be rewritten as long as the new value's 0 bits are a superset of the over-written values. For example, a nibble value may be erased to 1111, then written as 1110. Successive writes to that nibble can change it to 1010, then 0010, and finally 0000. Essentially, erasure sets all bits to 1, and programming can only clear bits to 0. Some file systems designed for flash devices make use of this rewrite capability, for example YAFFS1, to represent sector metadata. Other flash file systems, such as YAFFS2, never make use of this "rewrite" capability – they do a lot of extra work to meet a "write once rule".

Although data structures in flash memory cannot be updated in completely general ways, this allows members to be "removed" by marking them as invalid. This technique may need to be modified for multi-level cell devices, where one memory cell holds more than one bit.

Common flash devices such as USB flash drives and memory cards provide only a block-level interface, or flash translation layer (FTL), which writes to a different cell each time to wear-level the device. This prevents incremental writing within a block; however, it does help the device from being prematurely worn out by intensive write patterns.

Data retention

45nm NOR flash memory example of data retention varying with temperatures

Data stored on flash cells is steadily lost due to electron detrapping. The rate of loss increases exponentially as the absolute temperature increases. For example: For a 45 nm NOR flash, at 1000 hours, the threshold voltage (Vt) loss at 25°C is about half that at 90°C.

Memory wear

Another limitation is that flash memory has a finite number of program–erase cycles (typically written as P/E cycles). Micron Technology and Sun Microsystems announced an SLC NAND flash memory chip rated for 1,000,000 P/E cycles on 17 December 2008.

The guaranteed cycle count may apply only to block zero (as is the case with TSOP NAND devices), or to all blocks (as in NOR). This effect is mitigated in some chip firmware or file system drivers by counting the writes and dynamically remapping blocks in order to spread write operations between sectors; this technique is called wear leveling. Another approach is to perform write verification and remapping to spare sectors in case of write failure, a technique called bad block management (BBM). For portable consumer devices, these wear out management techniques typically extend the life of the flash memory beyond the life of the device itself, and some data loss may be acceptable in these applications. For high-reliability data storage, however, it is not advisable to use flash memory that would have to go through a large number of programming cycles. This limitation also exists for "read-only" applications such as thin clients and routers, which are programmed only once or at most a few times during their lifetimes, due to read disturb (see below).

In December 2012, Taiwanese engineers from Macronix revealed their intention to announce at the 2012 IEEE International Electron Devices Meeting that they had figured out how to improve NAND flash storage read/write cycles from 10,000 to 100 million cycles using a "self-healing" process that used a flash chip with "onboard heaters that could anneal small groups of memory cells." The built-in thermal annealing was to replace the usual erase cycle with a local high temperature process that not only erased the stored charge, but also repaired the electron-induced stress in the chip, giving write cycles of at least 100 million. The result was to be a chip that could be erased and rewritten over and over, even when it should theoretically break down. As promising as Macronix's breakthrough might have been for the mobile industry, however, there were no plans for a commercial product featuring this capability to be released any time in the near future.

Read disturb

The method used to read NAND flash memory can cause nearby cells in the same memory block to change over time (become programmed). This is known as read disturb. The threshold number of reads is generally in the hundreds of thousands of reads between intervening erase operations. If reading continually from one cell, that cell will not fail but rather one of the surrounding cells will on a subsequent read. To avoid the read disturb problem the flash controller will typically count the total number of reads to a block since the last erase. When the count exceeds a target limit, the affected block is copied over to a new block, erased, then released to the block pool. The original block is as good as new after the erase. If the flash controller does not intervene in time, however, a read disturb error will occur with possible data loss if the errors are too numerous to correct with an error-correcting code.

X-ray effects

Most flash ICs come in ball grid array (BGA) packages, and even the ones that do not are often mounted on a PCB next to other BGA packages. After PCB assembly, boards with BGA packages are often X-rayed to see if the balls are making proper connections to the proper pad, or if the BGA needs rework. These X-rays can erase programmed bits in a flash chip (convert programmed "0" bits into erased "1" bits). Erased bits ("1" bits) are not affected by X-rays.

Some manufacturers are now making X-ray-proof SD and USB memory devices.

Low-level access

The low-level interface to flash memory chips differs from those of other memory types such as DRAM, ROM, and EEPROM, which support bit-alterability (both zero to one and one to zero) and random access via externally accessible address buses.

NOR memory has an external address bus for reading and programming. For NOR memory, reading and programming are random-access, and unlocking and erasing are block-wise. For NAND memory, reading and programming are page-wise, and unlocking and erasing are block-wise.

NOR memories

NOR flash by Intel

Reading from NOR flash is similar to reading from random-access memory, provided the address and data bus are mapped correctly. Because of this, most microprocessors can use NOR flash memory as execute in place (XIP) memory, meaning that programs stored in NOR flash can be executed directly from the NOR flash without needing to be copied into RAM first. NOR flash may be programmed in a random-access manner similar to reading. Programming changes bits from a logical one to a zero. Bits that are already zero are left unchanged. Erasure must happen a block at a time, and resets all the bits in the erased block back to one. Typical block sizes are 64, 128, or 256 KiB.

Bad block management is a relatively new feature in NOR chips. In older NOR devices not supporting bad block management, the software or device driver controlling the memory chip must correct for blocks that wear out, or the device will cease to work reliably.

The specific commands used to lock, unlock, program, or erase NOR memories differ for each manufacturer. To avoid needing unique driver software for every device made, special Common Flash Memory Interface (CFI) commands allow the device to identify itself and its critical operating parameters.

Besides its use as random-access ROM, NOR flash can also be used as a storage device, by taking advantage of random-access programming. Some devices offer read-while-write functionality so that code continues to execute even while a program or erase operation is occurring in the background. For sequential data writes, NOR flash chips typically have slow write speeds, compared with NAND flash.

Typical NOR flash does not need an error correcting code.

NAND memories

NAND flash architecture was introduced by Toshiba in 1989. These memories are accessed much like block devices, such as hard disks. Each block consists of a number of pages. The pages are typically 512, 2,048, or 4,096 bytes in size. Associated with each page are a few bytes (typically 1/32 of the data size) that can be used for storage of an error correcting code (ECC) checksum.

Typical block sizes include:

• 32 pages of 512+16 bytes each for a block size (effective) of 16 KiB
• 64 pages of 2,048+64 bytes each for a block size of 128 KiB
• 64 pages of 4,096+128 bytes each for a block size of 256 KiB
• 128 pages of 4,096+128 bytes each for a block size of 512 KiB
• 2048 pages of 16,386+128 bytes each for a block size of 32768 KiB

Modern NAND flash may have erase block size between 1 MiB to 128 MiB. While reading and programming is performed on a page basis, erasure can only be performed on a block basis. Since changing a cell from 0 to 1 requires erasing an entire block instead of just modifying some pages, making changes to the data of a block may in reality be a read-erase-write (REW) or read-modify-erase-write (RMEW) process, where the new data is actually moved to another block.

NAND devices also require bad block management by the device driver software or by the flash memory controller chip. Some SD cards, for example, include controller circuitry to perform bad block management and wear leveling. When a logical block is accessed by high-level software, it is mapped to a physical block by the device driver or controller. A number of blocks on the flash chip may be set aside for storing mapping tables to deal with bad blocks, or the system may simply check each block at power-up to create a bad block map in RAM. The overall memory capacity gradually shrinks as more blocks are marked as bad.

NAND relies on ECC to compensate for bits that may spontaneously fail during normal device operation. A typical ECC will correct a one-bit error in each 2048 bits (256 bytes) using 22 bits of ECC, or a one-bit error in each 4096 bits (512 bytes) using 24 bits of ECC. If the ECC cannot correct the error during read, it may still detect the error. When doing erase or program operations, the device can detect blocks that fail to program or erase and mark them bad. The data is then written to a different, good block, and the bad block map is updated.

Hamming codes are the most commonly used ECC for SLC NAND flash. Reed–Solomon codes and BCH codes (Bose–Chaudhuri–Hocquenghem codes) are commonly used ECC for MLC NAND flash. Some MLC NAND flash chips internally generate the appropriate BCH error correction codes.

Most NAND devices are shipped from the factory with some bad blocks. These are typically marked according to a specified bad block marking strategy. By allowing some bad blocks, manufacturers achieve far higher yields than would be possible if all blocks had to be verified to be good. This significantly reduces NAND flash costs and only slightly decreases the storage capacity of the parts.

When executing software from NAND memories, virtual memory strategies are often used: memory contents must first be paged or copied into memory-mapped RAM and executed there (leading to the common combination of NAND + RAM). A memory management unit (MMU) in the system is helpful, but this can also be accomplished with overlays. For this reason, some systems will use a combination of NOR and NAND memories, where a smaller NOR memory is used as software ROM and a larger NAND memory is partitioned with a file system for use as a non-volatile data storage area.

NAND sacrifices the random-access and execute-in-place advantages of NOR. NAND is best suited to systems requiring high capacity data storage. It offers higher densities, larger capacities, and lower cost. It has faster erases, sequential writes, and sequential reads.

Further information on the NAND flash memory or SSD operation: Copyback

Standardization

A group called the Open NAND Flash Interface Working Group (ONFI) has developed a standardized low-level interface for NAND flash chips. This allows interoperability between conforming NAND devices from different vendors. The ONFI specification version 1.0^[123] was released on 28 December 2006. It specifies:

• A standard physical interface (pinout) for NAND flash in TSOP-48, WSOP-48, LGA-52, and BGA-63 packages
• A standard command set for reading, writing, and erasing NAND flash chips
• A mechanism for self-identification (comparable to the serial presence detection feature of SDRAM memory modules)

The ONFI group is supported by major NAND flash manufacturers, including Hynix, Intel, Micron Technology, and Numonyx, as well as by major manufacturers of devices incorporating NAND flash chips.

Two major flash device manufacturers, Toshiba and Samsung, have chosen to use an NAND flash interface of their own design known as Toggle Mode (and now Toggle). This interface isn't pin-to-pin compatible with the ONFI specification. The result is that a product designed for one vendor's devices may not be able to use another vendor's devices.

A group of vendors, including Intel, Dell, and Microsoft, formed a Non-Volatile Memory Host Controller Interface (NVMHCI) Working Group. The goal of the group is to provide standard software and hardware programming interfaces for nonvolatile memory subsystems, including the "flash cache" device connected to the PCI Express bus.

Distinction between NOR and NAND flash

NOR and NAND flash differ in two important ways:

• The connections of the individual memory cells are different.
• The interface provided for reading and writing the memory is different; NOR allows random access as it can be either byte-addressable or word-addressable, with words being for example 32 bits long, while NAND allows only page access.

NOR and NAND flash get their names from the structure of the interconnections between memory cells. In NOR flash, cells are connected in parallel to the bit lines, allowing cells to be read and programmed individually. The parallel connection of cells resembles the parallel connection of transistors in a CMOS NOR gate. In NAND flash, cells are connected in series, resembling a CMOS NAND gate. The series connections consume less space than parallel ones, reducing the cost of NAND flash. It does not, by itself, prevent NAND cells from being read and programmed individually.

Each NOR flash cell is larger than a NAND flash cell – 10 F² vs 4 F² –  even when using exactly the same semiconductor device fabrication and so each transistor, contact, etc. is exactly the same size – because NOR flash cells require a separate metal contact for each cell.

Because of the series connection and removal of wordline contacts, a large grid of NAND flash memory cells will occupy perhaps only 60% of the area of equivalent NOR cells (assuming the same CMOS process resolution, for example, 130 nm, 90 nm, or 65 nm). NAND flash's designers realized that the area of a NAND chip, and thus the cost, could be further reduced by removing the external address and data bus circuitry. Instead, external devices could communicate with NAND flash via sequential-accessed command and data registers, which would internally retrieve and output the necessary data. This design choice made random-access of NAND flash memory impossible, but the goal of NAND flash was to replace mechanical hard disks, not to replace ROMs.

The first GSM phones and many feature phones had NOR flash memory, from which processor instructions could be executed directly in an execute-in-place architecture and allowed for short boot times. With smartphones, NAND flash memory was adopted as it has larger storage capacities and lower costs, but causes longer boot times because instructions cannot be executed from it directly, and must be copied to RAM memory first before execution.

Attribute	NAND	NOR
Main application	File storage	Code execution
Storage capacity	Higher	Lower
Cost per bit	Lower	Higher
Active power	Lower	Higher
Standby power	Higher	Lower
Write speed	Faster	Slower
Random read speed	Slower	Faster
Execute in place (XIP)	No	Yes
Reliability	Lower	Higher
Required flash memory controller	Usually Yes	No

Write endurance

The write endurance of SLC floating-gate NOR flash is typically equal to or greater than that of NAND flash, while MLC NOR and NAND flash have similar endurance capabilities. Examples of endurance cycle ratings listed in datasheets for NAND and NOR flash, as well as in storage devices using flash memory, are provided.

Type of flash memory	Endurance rating (erases per block)	Example(s) of flash memory or storage device
SLC NAND	50,000–100,000	Samsung OneNAND KFW4G16Q2M, Toshiba SLC NAND flash chips, Transcend SD500, Fujitsu S26361-F3298
MLC NAND	5,000–10,000 for medium-capacity; 1,000 to 3,000 for high-capacity	Samsung K9G8G08U0M (example for medium-capacity applications), Memblaze PBlaze4, ADATA SU900, Mushkin Reactor
TLC NAND	1,000	Samsung SSD 840
QLC NAND	Unknown	SanDisk X4 NAND flash SD cards
3D SLC NAND	>100,000	Samsung Z-NAND
3D MLC NAND	6,000–40,000	Samsung SSD 850 PRO, Samsung SSD 845DC PRO, Samsung 860 PRO
3D TLC NAND	1,500–5,000	Samsung SSD 850 EVO, Samsung SSD 845DC EVO, Crucial MX300，Memblaze PBlaze5 900, Memblaze PBlaze5 700, Memblaze PBlaze5 910/916, Memblaze PBlaze5 510/516,ADATA SX 8200 PRO (also being sold under "XPG Gammix" branding, model S11 PRO)
3D QLC NAND	100–1,500	Samsung SSD 860 QVO SATA, Intel SSD 660p, Micron 5210 ION, Crucial P1, Samsung SSD BM991 NVMe
3D PLC NAND	Unknown	In development by SK Hynix (formerly Intel) and Kioxia (formerly Toshiba Memory).
SLC (floating- gate) NOR	100,000–1,000,000	Numonyx M58BW (Endurance rating of 100,000 erases per block); Spansion S29CD016J (Endurance rating of 1,000,000 erases per block)
MLC (floating- gate) NOR	100,000	Numonyx J3 flash
3D SLC NOR	>1,000,000
3D MLC NOR	100,000-1,000,000

However, by applying certain algorithms and design paradigms, such as wear leveling, flash over-provisioning and high-quality flash memory (such as pSLC and eTLC), the endurance of a storage system can be tuned to serve specific requirements.

In order to compute the longevity of the NAND flash, one must account for the size of the memory chip, the type of memory (e.g. SLC/MLC/TLC), and use pattern. Industrial NAND and server NAND are in demand due to their capacity, longer endurance and reliability in sensitive environments.

As the number of bits per cell increases, performance and life of NAND flash may degrade, increasing random read times to 100μs for TLC NAND which is 4 times the time required in SLC NAND, and twice the time required in MLC NAND, for random reads.

Flash file systems

Main article: Flash file system

Because of the particular characteristics of flash memory, it is best used with either a controller to perform wear leveling and error correction or specifically designed flash file systems, which spread writes over the media and deal with the long erase times of NOR flash blocks. The basic concept behind flash file systems is the following: when the flash store is to be updated, the file system will write a new copy of the changed data to a fresh block, remap the file pointers, then erase the old block later when it has time.

In practice, flash file systems are used only for memory technology devices (MTDs), which are embedded flash memories that do not have a controller. Removable flash memory cards, SSDs, eMMC/eUFS chips and USB flash drives have built-in controllers to perform wear leveling and error correction so use of a specific flash file system may not add benefit.

Capacity

Multiple chips are often arrayed or die stacked to achieve higher capacities for use in consumer electronic devices such as multimedia players or GPSs. The capacity scaling (increase) of flash chips used to follow Moore's law because they are manufactured with many of the same integrated circuits techniques and equipment. Since the introduction of 3D NAND, scaling is no longer necessarily associated with Moore's law since ever smaller transistors (cells) are no longer used.

Consumer flash storage devices typically are advertised with usable sizes expressed as a small integer power of two (2, 4, 8, etc.) and a conventional designation of megabytes (MB) or gigabytes (GB); e.g., 512 MB, 8 GB. This includes SSDs marketed as hard drive replacements, in accordance with traditional hard drives, which use decimal prefixes. Thus, an SSD marked as "64 GB" is at least 64 × 1000³ bytes (64 GB). Most users will have slightly less capacity than this available for their files, due to the space taken by file system metadata and because some operating systems report SSD capacity using binary prefixes which are somewhat larger than conventional prefixes .

The flash memory chips inside them are sized in strict binary multiples, but the actual total capacity of the chips is not usable at the drive interface. It is considerably larger than the advertised capacity in order to allow for distribution of writes (wear leveling), for sparing, for error correction codes, and for other metadata needed by the device's internal firmware.

In 2005, Toshiba and SanDisk developed a NAND flash chip capable of storing 1 GB of data using multi-level cell (MLC) technology, capable of storing two bits of data per cell. In September 2005, Samsung Electronics announced that it had developed the world's first 2 GB chip.

In March 2006, Samsung announced flash hard drives with capacity of 4 GB, essentially the same order of magnitude as smaller laptop hard drives, and in September 2006, Samsung announced an 8 GB chip produced using a 40 nm manufacturing process. In January 2008, SanDisk announced availability of their 16 GB MicroSDHC and 32 GB SDHC Plus cards.

More recent flash drives (as of 2012) have much greater capacities, holding 64, 128, and 256 GB.

A joint development at Intel and Micron will allow the production of 32-layer 3.5 terabyte (TB) NAND flash sticks and 10 TB standard-sized SSDs. The device includes 5 packages of 16 × 48 GB TLC dies, using a floating gate cell design.

Flash chips continue to be manufactured with capacities under or around 1 MB (e.g. for BIOS-ROMs and embedded applications).

In July 2016, Samsung announced the 4 TB Samsung 850 EVO which utilizes their 256 Gbit 48-layer TLC 3D V-NAND. In August 2016, Samsung announced a 32 TB 2.5-inch SAS SSD based on their 512 Gbit 64-layer TLC 3D V-NAND. Further, Samsung expects to unveil SSDs with up to 100 TB of storage by 2020.

Transfer rates

Flash memory devices are typically much faster at reading than writing. Performance also depends on the quality of storage controllers, which become more critical when devices are partially full. Even when the only change to manufacturing is die-shrink, the absence of an appropriate controller can result in degraded speeds.

Applications

Serial flash

Serial Flash: Silicon Storage Tech SST25VF080B

Serial flash is a small, low-power flash memory that provides only serial access to the data - rather than addressing individual bytes, the user reads or writes large contiguous groups of bytes in the address space serially. Serial Peripheral Interface Bus (SPI) is a typical protocol for accessing the device. When incorporated into an embedded system, serial flash requires fewer wires on the PCB than parallel flash memories, since it transmits and receives data one bit at a time. This may permit a reduction in board space, power consumption, and total system cost.

There are several reasons why a serial device, with fewer external pins than a parallel device, can significantly reduce overall cost:

• Many ASICs are pad-limited, meaning that the size of the die is constrained by the number of wire bond pads, rather than the complexity and number of gates used for the device logic. Eliminating bond pads thus permits a more compact integrated circuit, on a smaller die; this increases the number of dies that may be fabricated on a wafer, and thus reduces the cost per die.
• Reducing the number of external pins also reduces assembly and packaging costs. A serial device may be packaged in a smaller and simpler package than a parallel device.
• Smaller and lower pin-count packages occupy less PCB area.
• Lower pin-count devices simplify PCB routing.

There are two major SPI flash types. The first type is characterized by small blocks and one internal SRAM block buffer allowing a complete block to be read to the buffer, partially modified, and then written back (for example, the Atmel AT45 DataFlash or the Micron Technology Page Erase NOR Flash). The second type has larger sectors where the smallest sectors typically found in this type of SPI flash are 4 KB, but they can be as large as 64 KB. Since this type of SPI flash lacks an internal SRAM buffer, the complete block must be read out and modified before being written back, making it slow to manage. However, the second type is cheaper than the first and is therefore a good choice when the application is code shadowing.

The two types are not easily exchangeable, since they do not have the same pinout, and the command sets are incompatible.

Most FPGAs are based on SRAM configuration cells and require an external configuration device, often a serial flash chip, to reload the configuration bitstream every power cycle.

Firmware storage

With the increasing speed of modern CPUs, parallel flash devices are often much slower than the memory bus of the computer they are connected to. Conversely, modern SRAM offers access times below 10 ns, while DDR2 SDRAM offers access times below 20 ns. Because of this, it is often desirable to shadow code stored in flash into RAM; that is, the code is copied from flash into RAM before execution, so that the CPU may access it at full speed. Device firmware may be stored in a serial flash chip, and then copied into SDRAM or SRAM when the device is powered-up. Using an external serial flash device rather than on-chip flash removes the need for significant process compromise (a manufacturing process that is good for high-speed logic is generally not good for flash and vice versa). Once it is decided to read the firmware in as one big block it is common to add compression to allow a smaller flash chip to be used. Since 2005, many devices use serial NOR flash to deprecate parallel NOR flash for firmware storage. Typical applications for serial NOR flash include storing firmware for hard drives, BIOS, Option ROM of expansion cards, DSL modems, etc.

Flash memory as a replacement for hard drives

Main article: Solid-state drive

An Intel mSATA SSD in 2020

One more recent application for flash memory is as a replacement for hard disks. Flash memory does not have the mechanical limitations and latencies of hard drives, so a solid-state drive (SSD) is attractive in terms of speed, noise, power consumption, and reliability. Flash drives are gaining traction as mobile device secondary storage devices; they are also used as substitutes for hard drives in high-performance desktop computers and some servers with RAID and SAN architectures.

There remain some aspects of flash-based SSDs that make them unattractive. The cost per gigabyte of flash memory remains significantly higher than that of hard disks. Also, flash memory has a finite number of P/E (program/erase) cycles, but this seems to be currently under control since warranties on flash-based SSDs are approaching those of current hard drives. In addition, deleted files on SSDs can remain for an indefinite period of time before being overwritten by fresh data; erasure or shred techniques or software that work well on magnetic hard disk drives have no effect on SSDs, compromising security and forensic examination. However, due to the so-called TRIM command employed by most solid state drives, which marks the logical block addresses occupied by the deleted file as unused to enable garbage collection, data recovery software is not able to restore files deleted from such.

For relational databases or other systems that require ACID transactions, even a modest amount of flash storage can offer vast speedups over arrays of disk drives.

In May 2006, Samsung Electronics announced two flash-memory based PCs, the Q1-SSD and Q30-SSD were expected to become available in June 2006, both of which used 32 GB SSDs, and were at least initially available only in South Korea. The Q1-SSD and Q30-SSD launch was delayed and finally was shipped in late August 2006.

The first flash-memory based PC to become available was the Sony Vaio UX90, announced for pre-order on 27 June 2006 and began to be shipped in Japan on 3 July 2006 with a 16 GB flash memory hard drive. In late September 2006 Sony upgraded the flash-memory in the Vaio UX90 to 32 GB.

A solid-state drive was offered as an option with the first MacBook Air introduced in 2008, and from 2010 onwards, all models were shipped with an SSD. Starting in late 2011, as part of Intel's Ultrabook initiative, an increasing number of ultra-thin laptops are being shipped with SSDs standard.

There are also hybrid techniques such as hybrid drive and ReadyBoost that attempt to combine the advantages of both technologies, using flash as a high-speed non-volatile cache for files on the disk that are often referenced, but rarely modified, such as application and operating system executable files.

On smartphones, the NAND flash products are used as file storage device, for example, eMMC and eUFS.

Flash memory as RAM

As of 2012, there are attempts to use flash memory as the main computer memory, DRAM.

Archival or long-term storage

Floating-gate transistors in the flash storage device hold charge which represents data. This charge gradually leaks over time, leading to an accumulation of logical errors, also known as "bit rot" or "bit fading".

Data retention

It is unclear how long data on flash memory will persist under archival conditions (i.e., benign temperature and humidity with infrequent access with or without prophylactic rewrite). Datasheets of Atmel's flash-based "ATmega" microcontrollers typically promise retention times of 20 years at 85 °C (185 °F) and 100 years at 25 °C (77 °F).

The retention span varies among types and models of flash storage. When supplied with power and idle, the charge of the transistors holding the data is routinely refreshed by the firmware of the flash storage. The ability to retain data varies among flash storage devices due to differences in firmware, data redundancy, and error correction algorithms.

An article from CMU in 2015 states "Today's flash devices, which do not require flash refresh, have a typical retention age of 1 year at room temperature." And that retention time decreases exponentially with increasing temperature. The phenomenon can be modeled by the Arrhenius equation.

While flash storage retains data for a longer time if stored at colder temperatures, a higher but not extreme temperature while writing reduces stress and wear on the drive, given that electrons are able to flow more easily, according to Tim Schulte, Pranav Kalavade, and Johnmichael Hands from Intel.

FPGA configuration

Some FPGAs are based on flash configuration cells that are used directly as (programmable) switches to connect internal elements together, using the same kind of floating-gate transistor as the flash data storage cells in data storage devices.

Industry

See also: Semiconductor industry

One source states that, in 2008, the flash memory industry includes about US$9.1 billion in production and sales. Other sources put the flash memory market at a size of more than US$20 billion in 2006, accounting for more than eight percent of the overall semiconductor market and more than 34 percent of the total semiconductor memory market. In 2012, the market was estimated at $26.8 billion. It can take up to 10 weeks to produce a flash memory chip.

Manufacturers

Main articles: List of flash memory controller manufacturers and List of solid-state drive manufacturers

The following were the largest NAND flash memory manufacturers, as of the third quarter of 2025.

1. Samsung Electronics – 30%
2. SK Hynix – 20%
3. Kioxia – 14%
4. Micron Technology – 13%
5. YMTC – 13%
6. Western Digital Corporation – 11%

Notes: Samsung remains the largest NAND flash memory manufacturer as of Q3 2025.

Kioxia spun out and got renamed of Toshiba in 2018/2019.